JPS6072016U - noise reduction device - Google Patents

noise reduction device

Info

Publication number
JPS6072016U
JPS6072016U JP16260083U JP16260083U JPS6072016U JP S6072016 U JPS6072016 U JP S6072016U JP 16260083 U JP16260083 U JP 16260083U JP 16260083 U JP16260083 U JP 16260083U JP S6072016 U JPS6072016 U JP S6072016U
Authority
JP
Japan
Prior art keywords
circuit
noise reduction
reduction device
reverberation
gain switching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16260083U
Other languages
Japanese (ja)
Inventor
関口　紀之
梶田　勝
Original Assignee
日本圧電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本圧電気株式会社 filed Critical 日本圧電気株式会社
Priority to JP16260083U priority Critical patent/JPS6072016U/en
Publication of JPS6072016U publication Critical patent/JPS6072016U/en
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)
  • Amplifiers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例の回路図、第２図は本考案の
他の実施例の一部の回路図である。 １・・・入力端子、２・・・出力端子、３，５・・・オ
ペアンプ、４・・・リバーブレーションユニット、１０
・・・整流回路、１１．１６・・・トランジスタ、１２
，１３．１４・・・抵抗器、１５・・・利得切替回路。FIG. 1 is a circuit diagram of one embodiment of the present invention, and FIG. 2 is a partial circuit diagram of another embodiment of the present invention. 1... Input terminal, 2... Output terminal, 3, 5... Operational amplifier, 4... Reverberation unit, 10
... Rectifier circuit, 11.16 ... Transistor, 12
, 13.14...Resistor, 15... Gain switching circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 遅延回路または残響回路を有する増幅器において、前記
遅延回路または残響回路の入力側と出力側の間に、整流
回路と該整流回路の出力電圧によって利得切替を行なう
利得切替回路とを、前記遅延回路または残響回路に並列
関係に接続したこと−を特徴とするノイズ低減装置。In an amplifier having a delay circuit or a reverberation circuit, a rectifier circuit and a gain switching circuit that performs gain switching according to the output voltage of the rectification circuit are provided between the input side and the output side of the delay circuit or reverberation circuit. A noise reduction device characterized by being connected in parallel to a reverberation circuit.
JP16260083U 1983-10-20 1983-10-20 noise reduction device Pending JPS6072016U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16260083U JPS6072016U (en) 1983-10-20 1983-10-20 noise reduction device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16260083U JPS6072016U (en) 1983-10-20 1983-10-20 noise reduction device

Publications (1)

Publication Number Publication Date
JPS6072016U true JPS6072016U (en) 1985-05-21

Family

ID=30357013

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16260083U Pending JPS6072016U (en) 1983-10-20 1983-10-20 noise reduction device

Country Status (1)

Country Link
JP (1) JPS6072016U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55135430A (en) * 1979-04-09 1980-10-22 Matsushita Electric Ind Co Ltd Radio receiver

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55135430A (en) * 1979-04-09 1980-10-22 Matsushita Electric Ind Co Ltd Radio receiver

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