JPS63102328A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPS63102328A
JPS63102328A JP61248763A JP24876386A JPS63102328A JP S63102328 A JPS63102328 A JP S63102328A JP 61248763 A JP61248763 A JP 61248763A JP 24876386 A JP24876386 A JP 24876386A JP S63102328 A JPS63102328 A JP S63102328A
Authority
JP
Japan
Prior art keywords
semiconductor chip
leadframe
high molecular
polymer adhesive
bonding agent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61248763A
Other languages
English (en)
Inventor
Hirobumi Koyama
小山　博文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP61248763A priority Critical patent/JPS63102328A/ja
Publication of JPS63102328A publication Critical patent/JPS63102328A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、リードフレームと半導体チップとの接続に高
分子接着剤を用いる場合の半導体装置の製造方法に関す
るものである。
従来の技術 従来、半導体チップの支持体への接着には、金−シリコ
ン共晶を主に用いてきた。これは、接着材料である金−
シリコンが安定であり、不純物発生の心配が少ないため
であった。しかし、この方式によれば、サイズの大きい
チップを均一に接着することができず、応力の不均一を
生じ問題を起こす。また、リードフレームに銅を用いた
場合にも、金−シリコン共晶による接着手段は使えない
。このような場合、第１図に示すようにリードフレーム
１と半導体チップ２との接着には、銀エポキシペースト
等の高分子接着剤３を用いていた。なお、第１図におい
て、ワイヤ４はリードフレーム１と半導体チップ２とを
接続する手段である。
発明が解決しようとする問題点 しかしながら、リードフレーム１と半導体チップ２とを
高分子接着剤で接着する過程、あるいは同接着後、ワイ
ヤ４による接続時には、半導体チップ２の周辺を高温と
するため、高分子接着剤３が熱によって分解し、チップ
表面が汚染され、その後の湿気の浸入と共に半導体チッ
プ２上のアルミニウム配線層等に腐食が発生する。
本発明はこの点を考慮し、耐湿性を上げることを目的と
している。
問題点を解決するための手段 本発明は、上記問題点を解決するため、リードフレーム
と半導体チップとを高分子接着剤を用いて接着する過程
もしくは、リードフレームと上記半導体チップとのワイ
ヤボンディングの過程で排気を行なう方法である。
作用 本発明により、湿気の浸入に伴なうアルミニウム配線等
の腐食を押えることができる。
実施例 第２図は、ワイヤボンド温度とプレッシャーフッカテス
ト（Ｐ、Ｃ，Ｔ）による累棲故障率を示した図である。
高分子接着剤を用いた場合、ワイヤボンド温度が高くな
る程、故障は早く発生する。またワイヤボンド温度を低
（すると、従来の金−シリコン共晶方式と同等の耐湿性
を有する。
これより、高分子接着剤を用いたリードフレームと半導
体チップとの接着による半導体装置の耐湿性劣化には、
ワイヤボンド温度が太き（関与することがわかる。特に
上記高分子接着剤の熱分解温度の影響が太き（、高分子
接着剤の熱分解温度以下の温度で上記リードフレームと
上記半導体チップとをワイヤボンディングすれば、半導
体装置の耐湿性は向上する。
また、高分子接着剤の分解ガス中に放置した半導体チッ
プを同様に組立てた場合、更に耐湿性が劣化する。これ
より、高分子接着剤を用いてリードフレームとシリコン
チップとを接続する場合に、分解ガスの排気をしなけれ
ば、半導体装置に高分子接着剤の分解ガスが付着し耐湿
性劣化を更に加速することがわかる。したがって、高分
子接着剤を用いたリードフレームと半導体チップの接着
の際には、分解ガスの排気を十分行なうことが有効であ
る。
なお、排気工程を付加したことによる歩留りの低下、金
ワイヤーとアルミニウムとの共晶状態には、何ら変化な
（良好である。
発明の効果 以上の説明で明らかなように、本発明によれば、高分子
接着剤を用いた半導体装置の耐湿性を劣化させないこと
から、実用上極めて有効である。
【図面の簡単な説明】
第１図は高分子接着剤を用いてリードフレームとシリコ
ンチップとを接着している様子を示す断面図、第２図は
ワイヤボンド温度とプレッシャーフッカテスト（Ｐ、Ｃ
，Ｔ）による累積故障を示す図である。 １・・・・・・リードフレーム、２・・・・・・半導体
チップ、３・・・・・・高分子接着剤、４・・・・・・
ワイヤ。 代理人の氏名　弁理士　中尾敏男　ほか１２富１図 第　２　図 拭取晴間（）ｌ）

Claims (1)

    【特許請求の範囲】
  1. リードフレームと半導体チップとを高分子接着剤を用い
    て接着する過程もしくは、上記高分子接着剤で接着した
    のち、リードフレームと上記半導体チップとをワイヤボ
    ンディングする過程で排気することを特徴とする半導体
    装置の製造方法。
JP61248763A 1986-10-20 1986-10-20 半導体装置の製造方法 Pending JPS63102328A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61248763A JPS63102328A (ja) 1986-10-20 1986-10-20 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61248763A JPS63102328A (ja) 1986-10-20 1986-10-20 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
JPS63102328A true JPS63102328A (ja) 1988-05-07

Family

ID=17183011

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61248763A Pending JPS63102328A (ja) 1986-10-20 1986-10-20 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS63102328A (ja)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57192040A (en) * 1981-05-22 1982-11-26 Toshiba Corp Wire bonding method for semiconductor device
JPS61105850A (ja) * 1984-10-30 1986-05-23 Mitsubishi Electric Corp ワイヤボンデイング方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57192040A (en) * 1981-05-22 1982-11-26 Toshiba Corp Wire bonding method for semiconductor device
JPS61105850A (ja) * 1984-10-30 1986-05-23 Mitsubishi Electric Corp ワイヤボンデイング方法

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