JPS6291442U - - Google Patents
Info
- Publication number
- JPS6291442U JPS6291442U JP18375185U JP18375185U JPS6291442U JP S6291442 U JPS6291442 U JP S6291442U JP 18375185 U JP18375185 U JP 18375185U JP 18375185 U JP18375185 U JP 18375185U JP S6291442 U JPS6291442 U JP S6291442U
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor package
- land portion
- output terminal
- solder resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims 3
- 239000004065 semiconductor Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
第１図は本考案パツケージの一例を示す縦断面
図、第２図は第１図の線部拡大図、第３図は第
２図の平面図、第４図は他の実施例の第２図と同
様図、第５図は従来のパツケージにおける第３図
と同様図である。
（符号の説明）、１……基板、２……スルーホ
ール、２１……ランド部分、２１１……周縁部、
３……入出力端子ピン、４……ソルダーレジスト
。
Fig. 1 is a vertical sectional view showing an example of the package of the present invention, Fig. 2 is an enlarged view of the lined part in Fig. 1, Fig. 3 is a plan view of Fig. 2, and Fig. 4 is a second embodiment of another embodiment. FIG. 5 is a diagram similar to FIG. 3 in a conventional package. (Explanation of symbols), 1... Board, 2... Through hole, 21... Land part, 211... Peripheral part,
3...Input/output terminal pin, 4...Solder resist.
Claims (1)
ピンを嵌入して成る半導体パツケージにおいて、
前記基板のスルーホールに連続するランド部分の
少なくとも周縁部がソルダーレジストにて被装さ
れ、ランド部分の周囲において基板の素地面が露
出しないようになされていることを特徴とする半
導体パツケージ。 In a semiconductor package in which input/output terminal pins are inserted into through holes in a plastic substrate,
A semiconductor package characterized in that at least a peripheral edge of a land portion continuous with a through-hole of the substrate is covered with a solder resist so that the base surface of the substrate is not exposed around the land portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18375185U JPS6291442U (en) | 1985-11-28 | 1985-11-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18375185U JPS6291442U (en) | 1985-11-28 | 1985-11-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6291442U true JPS6291442U (en) | 1987-06-11 |
Family
ID=31130779
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18375185U Pending JPS6291442U (en) | 1985-11-28 | 1985-11-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6291442U (en) |
-
1985
- 1985-11-28 JP JP18375185U patent/JPS6291442U/ja active Pending