JPS6287456U - - Google Patents
Info
- Publication number
- JPS6287456U JPS6287456U JP17932085U JP17932085U JPS6287456U JP S6287456 U JPS6287456 U JP S6287456U JP 17932085 U JP17932085 U JP 17932085U JP 17932085 U JP17932085 U JP 17932085U JP S6287456 U JPS6287456 U JP S6287456U
- Authority
- JP
- Japan
- Prior art keywords
- wiring pattern
- terminals
- integrated circuit
- group
- circuit package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第1図a,bは本考案の実施例を示す斜視図及
び側面図、第2図は本考案の実施例を示す上面図
、第3図は本考案の実施例を示す側面図、第4図
は本考案の応用例を示す平面図、第5図は従来の
集積回路パツケージの平面図である。
1……パツケージ、2……チツプ、3……ワイ
ヤ、4,4a,4b,7……電極、5a,5b…
…配線、6……導体膜、10,11……絶縁層、
R……抵抗。
Figures 1a and b are perspective views and side views showing an embodiment of the invention, Figure 2 is a top view showing an embodiment of the invention, Figure 3 is a side view showing an embodiment of the invention, and Figure 4 is a side view showing an embodiment of the invention. The figure is a plan view showing an application example of the present invention, and FIG. 5 is a plan view of a conventional integrated circuit package. 1... Package, 2... Chip, 3... Wire, 4, 4a, 4b, 7... Electrode, 5a, 5b...
... Wiring, 6 ... Conductor film, 10, 11 ... Insulating layer,
R...Resistance.
Claims (1)
搭載された集積回路チツプ上の入力端子へ接続す
る内部端子群と、端子間を相互に接続する配線パ
ターンとを有する集積回路パツケージにおいて、
前記2個の外部端子相互間を予め定めた特性イン
ピーダンスの配線パターンで接続し、更にこの配
線パターンと一つの内部端子を他の配線パターン
で接続することを特徴とする集積回路パツケージ
。 An integrated circuit package having a group of external terminals for external connection, a group of internal terminals connected to input terminals on an integrated circuit chip mounted on a predetermined location on a board, and a wiring pattern for interconnecting the terminals,
An integrated circuit package characterized in that the two external terminals are connected to each other by a wiring pattern having a predetermined characteristic impedance, and further, this wiring pattern and one internal terminal are connected to each other by another wiring pattern.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1985179320U JPH071845Y2 (en) | 1985-11-20 | 1985-11-20 | Integrated circuit package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1985179320U JPH071845Y2 (en) | 1985-11-20 | 1985-11-20 | Integrated circuit package |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6287456U true JPS6287456U (en) | 1987-06-04 |
JPH071845Y2 JPH071845Y2 (en) | 1995-01-18 |
Family
ID=31122273
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1985179320U Expired - Lifetime JPH071845Y2 (en) | 1985-11-20 | 1985-11-20 | Integrated circuit package |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH071845Y2 (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5685405U (en) * | 1979-11-30 | 1981-07-09 | ||
JPS5797660A (en) * | 1980-12-11 | 1982-06-17 | Fujitsu Ltd | High density structure |
-
1985
- 1985-11-20 JP JP1985179320U patent/JPH071845Y2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5685405U (en) * | 1979-11-30 | 1981-07-09 | ||
JPS5797660A (en) * | 1980-12-11 | 1982-06-17 | Fujitsu Ltd | High density structure |
Also Published As
Publication number | Publication date |
---|---|
JPH071845Y2 (en) | 1995-01-18 |
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