JPS6283676A - Ic testing system - Google Patents

Abstract

PURPOSE:To rapidly and easily form a test pattern, by performing a test by the use of input and output patterns stored in a pattern memory. CONSTITUTION:An actual circuit apparatus 20 having good quality LSI21 mounted thereto is operated and input and output patterns at this time are respectively stored in pattern memories 1, 2. An LSI tester 10 reads the pattern content of the memory 1 to supply the same to LSI12 to be measured. The output pattern LSI12 corresponding to this is compared with the pattern content of the memory 2 and the tester 10 judges whether LSI12 is good or not corresponding to coincidence and non-coincidence. By this constitution, the test pattern is easily and rapidly formed.

Description

[Detailed Description of the Invention] Technical Field The present invention relates to a test method for IC (peripheral circuit), and in particular to a test method for IC (peripheral circuit).
The present invention relates to an LSI test method using an I (Large Ju Model Integrated Circuit) tester.

Conventionally, in LSI testing of (Φ), ICs such as Sl are tested by creating a y-test pattern based on a certain standard.

The conventional test method described above sequentially tests all elements inside an LSI using a test pattern that determines regularity.)
It has become. Therefore, iJ 6 motion ('1
This has the disadvantage that an LSI that is determined to be good in an LSI testing machine may malfunction in an actual device and become a defective product because the patterns do not necessarily match and malfunctions due to pattern effects cannot be detected. 1゜In addition, since test data patterns for testing were traditionally created manually, there was also the drawback that pattern creation required a great deal of darkness and effort. It had become.

The present invention has been made to eliminate the drawbacks of the above-mentioned conventional devices, and its purpose is to improve the LSI actual device 4.
An object of the present invention is to provide an IC testing method that can test an LSI under test in an actual operating mode.

Another object of the present invention is to provide an IC test method that allows test patterns to be created in a short time without requiring any effort.

51! Structure of Sails According to the present invention, an input data pattern and an output data pattern at each terminal of the above 1c are respectively derived and stored from the actual circuit device 73 on which the IC (integrated circuit) to be tested is to be actually mounted. A memory is provided, and the input data pattern of the pattern memory is applied as a test pattern to the IC under test, and then 1! ′? The IC testing method is characterized in that the output data pattern of the IC under test is compared with the output data pattern of the pattern memory.

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

The figure is a block diagram of one embodiment of the present invention. Figure smell-
The input card gamer, memory 1, and memory 2 each have a sufficiently large storage capacity [11].
The actual circuit device 20 on which the LS under test 1-3112 is to be mounted has a non-defective memory 8121 which is the same as the LS under test 112. This good item 1. ,
SI 21 is connected to both memories 1゜2 and LSI socket 3, and the signal at the input terminal of socket 3 corresponding to the input of good LS121 is input to memory 1 through connection t+24, and corresponds to the output of good LSI 21. The signal from the output terminal J of the socket 3 is connected to the memory 2 by the connecting wire 5.
is input to. The output of the memory 1 is inputted to the pattern input terminal 131 of the I-8I test bay 10 through the connection line 6 and the output of the memory 2 through the connection line 7 and the connector 8. The above input/output υ to the memory 1.2 is controlled by the control unit 9.

The LSI tester 10' tests the LSI 12 under test mounted on the test stage controller 11 using the test pattern stored in the memory 1.
If the output of the LS 112 matches the output of the memory 2 once, it is determined to be good; if they do not match, it is determined to be defective.

More specifically, first, the actual circuit device 20 in which the non-defective LSI 21 is actually mounted is operated, and the non-defective product 1. ,,,
The input data pattern and output data pattern in S I 21 are stored in memories 1 and 2, respectively. After that, the input data pattern stored in memory 1 is
It is supplied to the LSI tester 10 as an I test data pattern and applied to the input of the LSI 12 under test. At this time, the output data pattern output from the LS under test 112 is compared with the data pattern stored in the LS 12. As a result of this comparison, if the two output data patterns match, it can be determined that the LSI 12 under test is a good product, and if they do not match, it can be determined that it is a defective product.

It is clear that the circuit element to be tested is not limited to 1-31, but can be applied to various ICs.

As described in detail, according to the present invention, Jj +
By using the operation pattern 1-3L as the test pattern for the 1-3L test machine, it is possible to test the LSI under test in the actual operation mode 'C', and the creation of the 1-2 pattern can be done in a short time and with less effort. The effect is that it can be done without any need.

[Brief explanation of drawings]

The figure is a block diagram of an embodiment of the invention. 1 Explanation of the symbol of the concave part 1.52...Memory 10... LSI tester 12...Acidic #LS I 20...Circuit device 21...Good LSI

Claims (1)

[Claims] A pattern memory is provided that derives and stores an input data pattern and an output data pattern at each terminal of the IC from an actual circuit device in which an IC (integrated circuit) under test is to be actually mounted, and the input data of the pattern memory is An IC testing method characterized in that a pattern is applied as test input data to the IC under test, and the output data pattern of the IC under test obtained at that time is compared with the output data pattern of the pattern memory. .