JP2906417B2 - Microcomputer test method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a microcomputer test method,
In particular, read-only memory (hereinafter referred to as ROM) and random
The present invention relates to a microcomputer test method in which an access memory (hereinafter, referred to as RAM), a programmable memory (hereinafter, referred to as PROM), and an interface circuit are incorporated in one chip.

[Conventional technology]

Generally, in the product inspection process of an integrated circuit, an operation test at a high temperature or a burn-in test for detecting an initial failure by operating the product in a high-temperature atmosphere for a long time to apply thermal and electrical stress to the product is performed. ing.

However, in a product having a complicated random gate such as a microcomputer, simply applying a power supply voltage fixes the operation state of the circuit, so that there is a portion in the circuit where electric stress is not applied.

In this case, if a clock signal is applied after resetting, the user program written in the ROM is executed.However, in the manufacturing process, the user's peripheral circuits are not connected and the program is not in an environment in which the program should operate. However, it is not possible to eliminate the parts that are not stressed by entering an infinite loop.

As a countermeasure, there is a method in which a program for operating the entire circuit of the microcomputer under test is created in advance, and the program is externally input to the microcomputer under test and executed to perform a burn-in test (hereinafter referred to as a dynamic Burn-in test).

FIG. 5 is a block diagram of an example of a conventional integrated circuit test apparatus.

Test apparatus for an integrated circuit, ROM, n pieces of the microcomputer Q ₁₁ to Q _1n with RAM and a serial interface circuit
The m test boards B _1c -B _{mc on} which are mounted are placed in a thermostat 1 heated by a heater 2, and a pattern output from a pattern signal generating circuit 4 c for inputting a power supply 3 and a pattern program signal S _pc of a pattern memory 5 c. data signal S _pD are supplied in parallel to the m × n of all tested microcomputer Q ₁₁ to Q _mn via the pattern data lines L _S than the wiring bundle of 10 several.

The microcomputer under test Q is stored in the pattern memory 5c.
₁₁ to Q and program for operating the entire internal circuit is stored in _mn, pattern signal generator circuit 4c the pattern memory
Receiving a pattern program signal S _pC from 5c, to generate a program pattern signal S _pD, total microcomputer Q ₁₁
Operate ~ Q _mn .

In this manner, a dynamic test for a predetermined time, which is a high-temperature dynamic test or a manufacturing process screening test, is performed.
A burn-in test was being conducted.

[Problems to be solved by the invention]

In the microcomputer test method described above, since the microcomputer is operated by supplying a program from the outside during the test, it is not possible to determine whether or not the microcomputer has become defective during the dynamic burn-in test. For this purpose, it is necessary to test all the functions of the microcomputer by using the LSI test apparatus after the dynamic burn-in test, and there is a disadvantage that much time is spent for determining the quality.

In contrast to the above-described conventional microcomputer test method, the present invention provides a microcomputer having a PROM for storing information on test results, while performing various tests such as a dynamic burn-in test. Since there is a means for writing to the PROM, there is a difference that the quality of the microcomputer can be determined only by reading the contents of the PROM after the test.

[Means for solving the problem]

The test method of the microcomputer according to the present invention includes a random access program built in the microcomputer under test by using a serial transfer means built in the microcomputer under test using a test program stored in a pattern memory provided in the test apparatus. Transferred to a memory, and the microcomputer under test self-executes the test program stored in the random access memory to test each component of the microcomputer under test. It is stored in a nonvolatile memory built in the microcomputer under test.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a microcomputer to be tested according to the first embodiment of the present invention. Tested microcomputer Q ₁₁ is a program ROM13 storing the CPU11 and the user program, and PROM17 storing information of the stored bootstrap ROM12 and RAM14 and the test results a program that operates via a serial interface circuit 15 having a receive buffer The peripheral circuit 16 is included.
Usually program ROM13 is selected, PROM 17 is a non-selective, but bootstrap ROM12 by the inverter I when the bootstrap ROM selection signal S _BR is input
There is selected, PROM 17 is selected by the selection signal S _BR.

FIG. 2 is a block diagram of a test apparatus in which the microcomputer of FIG. 1 is mounted, and a first embodiment of the present invention will be described below with reference to FIGS.

The test apparatus is composed of n microcomputers Q _{11 to} Q under test.
Each of the trial board B ₂ .about.B _{m to 1n} are configurations test boards B ₁ and similarly mounted receives a heparan program signal S _p to the input terminal, the series and outputs serial data signal S _SD from the output terminal The microcomputer under test Q ₁₁ through the data signal line l _SD
The receiving end T _SR of Q _mn has a supply pattern signal generating circuit 4. The terminals T _BR , T _R , T _C and T _SR in FIG. 1 are connected to the respective wirings l _BR , l _R , l _C and l _SD in FIG.

First, the inside of the thermostat 1 is heated to a high temperature (for example, 100
° C). Power supply 3 supplies a power supply voltage through the power line l _D and ground line to be tested microcomputer Q ₁₁ to Q _mn. Pattern signal generating circuit 4 is a clock signal S _C through the clock signal line l _C, bootstrap ROM bootstrap ROM selection signals of the bootstrap ROM selection signal S _BR through selection signal line l _BR entire microcomputer Q ₁₁ to Q _mn Transmit simultaneously to end _TBR .

Pattern signal when generating circuit 4 generates a reset signal S _R via the reset signal line l _R of the microcomputers Q ₁₁
~ _Qmn is the high level of the bootstrap ROM selection signal.
11 executes a program stored in the bootstrap ROM 12. The pattern signal generation circuit 4 outputs the reset signal S _R
Reads the pattern program S _P stored in the generation after the pattern memory 5, and outputs in series one bit in the serial data signal line l _SD. Each microcomputer Q ₁₁ to Q _mn receives serial data signal S _SD simultaneously using a serial interface circuit 15.

CPU11 sequentially from the receive buffer read signal S _RE is high level, the head address of the data read from the receiving buffer with the address signal lines l _A and the data signal line l _B RAM 14 according to a program stored in the bootstrap ROM12 Write. This processing is performed until reception of a predetermined number of bytes is completed. After that, the program branches to the start address of the RAM 14 and executes the program written in the RAM 14. With this program, the microcomputers under test Q _{11 to} Q _mn
Can be operated to perform the dynamic burn-in test.

If failure during testing occurred the program branches to an error handling routine, a write error information to PROM17 through the outputs of the PROM write signal S _PG data signal line l _B CPU 11,
The microcomputer under test in which the defect has occurred stops operating. Thus again select PROM17 to dynamic burn-in test after completion of the selection signal S _BR by LSI test device as a high level, the PROM read signal S _RD from CPU11
By reading the contents of the PROM 17, it can be determined whether or not the microcomputer under test has failed during the dynamic burn-in test, and it is not necessary to test all the functions of the microcomputer under test as in the conventional case.

FIG. 3 is a flowchart showing a test method of the microcomputer of the embodiment shown in FIGS. FIG. 3 will be described with reference to FIG. 1 and FIG.

Steps 101 to 108 show the procedure as described above. It is assumed that the PROM 17 has been initialized to the first "00 _H " (H represents hexadecimal notation). Program transferred to RAM14 of the test microcomputer Q ₁₁ to Q _mn first testing a CPU 11 (step 109). Here, if the operation of the CPU 11 is determined to be defective as a result of the test, the program jumps to an error processing routine stored in the RAM 14, and in the error processing routine, outputs the PROM write signal S _PG and outputs the data signal line l _B Error information “01” in PROM17 via
_H "is written. Thereafter, the microcomputer under test which has detected the defect stops its operation (step 112).

If the operation of the CPU 11 is determined to be normal, the program ROM 13 is tested next (step 111). When an operation failure is detected in the same manner as described above, error information "02 _H " is written in the PROM 17, and the microcomputer stops operation of the device under test in which the failure was detected (step 115). Program ROM 13
Is determined to be normal, the peripheral circuit 16 is tested next (step 114). When an operation failure is detected in the same manner as described above, the error information “03 _H ” is written into the PROM 17 and the microcomputer under test that has detected the failure stops operating (step 117). These series of processes are repeated within a predetermined time (step 118), and "FF _H " is written as information indicating a non-defective product in the PROM 17 of the microcomputer under test in which no defect was finally detected (step 118).
119). This completes the dynamic burn-in test.

Thereafter, if the contents of the PROMs 17 of the microcomputers under test Q _{11 to} Q _mn are read by the LSI test apparatus (step 120), it is not possible to immediately determine whether or not a failure has occurred by the dynamic burn-in test. For example PROM
If the data of 17 is “FF _H ”, it means that no failure occurred during the dynamic burn-in test, and “03 _H ”
If the peripheral circuit during the dynamic burn-in test
16 indicates that something went wrong. That is, it is not necessary to test all functions of the microcomputer under test after the dynamic burn-in test as in the related art.

In the present embodiment, each function of the microcomputer under test is tested in the order of the CPU, the program ROM, and the peripheral circuits, but this order is not particularly specified. Further, each information representative of the error information and good "01 _H ~03 _H",
Although “FF _H ” is set, specific numerical values are not particularly limited. Further, the PROM 17 is an ultraviolet erasable nonvolatile memory (EPROM) and an electrically erasable nonvolatile memory (EEPRO).
M), and the number of bytes is not limited.

FIG. 4 is a block diagram showing a second embodiment of the present invention. In the above-described first embodiment, the present invention is applied to a dynamic burn-in test of a microcomputer. In the second embodiment, the present invention is applied to a normal operation test at normal temperature. .

In FIG. 4, portions having the same functions as those in FIG. 2 are denoted by the same reference numerals. Is different from the second figure is that with a display device D ₁₁ to D _1n output terminal P of the boat circuit in which a plurality of the test microcomputer Q ₁₁ to Q _1n are built respectively.

As explained in detail in the first embodiment, first, the test for supply voltages from the power source 3 to the microcomputer Q ₁₁ to Q _1n, followed by the pattern signal generating circuit 4 is a bootstrap ROM selection signal S _BR output bootstrap ROM under test microcomputer Q ₁₁ to Q _1n are selected. Then the reset signal S _R is output, the reset signal S _R of release after bootstrap the ROM-stored program is run pattern program S _P is serial data signal line l via the _SD tested microcomputer Q ₁₁ is input to the reception terminal T _SR of serial interface circuits to Q _1n, built-in RAM
Is written to. Then the microcomputer under test Q ₁₁
To Q _1n executes self a program written in RAM, write the test results, such as a CPU, each function in a built-in PROM.

Here, the output terminal P of the boat circuit built in the microcomputer is used for those finally determined to be non-defective.
The program is configured to output a high level from. Display circuit D ₁₁ to D _1n indicates a non-defective by lit for the example LED or the like for detecting the high level. In this way, a plurality of microcomputers can be tested at once in a short time, and a system for testing can be used which is simpler than a normal LSI test apparatus.

〔The invention's effect〕

As described above, the present invention transfers the test program to the random access memory built in the microcomputer under test, executes the test program by itself, and writes the pass / fail judgment result to the nonvolatile memory. After performing various tests such as a dynamic burn-in test, pass / fail judgment can be made simply by reading the contents of the non-volatile memory, so that the test time for pass / fail judgment can be significantly reduced, and a system for testing can be further reduced. Since it can be greatly simplified, it leads to efficiency and cost reduction in the product inspection process, and there is an effect that an inexpensive microcomputer can be provided.

[Brief description of the drawings]

1 and 2 are a block diagram of a microcomputer under test and a block diagram of a test apparatus according to a first embodiment of the present invention, respectively, and FIG. 3 is a block diagram of the first embodiment of the present invention shown in FIG. 1 and FIG. FIG. 4 is a block diagram showing a second embodiment of the present invention, and FIG. 5 is a block diagram of a conventional integrated circuit test apparatus. 11 CPU, 12 Bootstrap ROM, 13 Program ROM, 14 RAM, 15 Serial interface circuit, 17 PROM, Q _{11 to} Q _mn Microcomputer,
T _SR ...... receiving end, D ₁₁ ~D _1n ...... display device.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-61-221837 (JP, A) JP-A-60-17543 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 11/22-11/26 G06F 15/78 510

Claims (1)

(57) [Claims] 1. A test program stored in a pattern memory provided in a test apparatus is transferred to a random access memory built in the microcomputer under test by using serial transfer means built in the microcomputer under test. The microcomputer under test is
Self-executing the test program stored in the access memory to test each component of the microcomputer under test, and storing information of the result of the test in a nonvolatile memory built in the microcomputer under test. A microcomputer test method.