JP3016755B2 - Inspection system that allows optional selection of integrated circuit elements mounted on the inspection board - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to semiconductor technology, and more particularly, to a burn-in inspection system capable of arbitrarily selecting a plurality of integrated circuit elements mounted on an inspection board.

[0002]

2. Description of the Related Art Generally, a semiconductor integrated circuit device is manufactured after manufacturing.
The highest probability of failure within 000 hours, 100
After 0 hours, the possibility of occurrence of a defect is reduced. In order to preliminarily search for an integrated circuit element having a short life and an initial failure, a semiconductor manufacturing company applies a thermal and electrical stress to the integrated circuit element to improve the reliability of a product supplied to a user. Inspection (burn-in t
est) is commonly performed.

The burn-in test is performed on an integrated circuit device packaged by an assembling process. Depending on the test method, a dynamic burn-in test or a static burn-in test is performed.
There are burn-in and monitor burn-in.
The static burn-in is a method of heating a heat by supplying only a power supply voltage to an integrated circuit device, and is often used for testing a linear integrated circuit device and a logic integrated circuit device. The dynamic burn-in is mainly used to detect an initial failure of a memory product, and applies a voltage, a signal, data or the like as in a state where an integrated circuit element is actually operating. In order to accelerate the voltage, an electric stress and a thermal stress are simultaneously applied to the integrated circuit device by setting a higher voltage. The monitor burn-in accelerates initial failure by applying electric and thermal stress to the integrated circuit element, and at the same time, tests the function of the integrated circuit element by measuring an electric signal output from the integrated circuit element. I do. According to the monitor burn-in, the function test of the integrated circuit device is performed at the same time, so that the burn-in test time can be optimized and the test cost can be reduced. At present, monitor burn-in is mainly used for testing integrated circuit elements, and is therefore also called memory burn-in.

[0004] Burn-in inspection is usually performed by using a large number of integrated circuit elements, for example, 128 on each of one or more inspection substrates.
A plurality of integrated circuit elements are mounted, the test substrate is placed in a temperature-controllable chamber, and thermal stress is applied to the integrated circuit elements to accelerate initial failure. On the other hand, in order to accelerate the initial failure by applying electric stress to the integrated circuit device mounted on the test board, the signal supply pins of the test device and the terminals of the 128 integrated circuit devices are connected in parallel to form a large number of integrated circuits. Electrical signals are simultaneously supplied to the circuit elements. The acceleration of the initial failure can be performed on a plurality of integrated circuit elements mounted on the test board at a time even if the number of pins of the test apparatus is limited.

[0005]

However, when inspecting the function of an integrated circuit element such as monitor burn-in, an output signal output from the integrated circuit element is measured using one inspection apparatus. It is not possible. Because,
In order to select an integrated circuit device in the function test, the test device
Although a scan signal is used, conventional monitor burn-in allows only one or two integrated circuit elements to be selected at a time.

The number of integrated circuit elements selected by the scan signal is limited by the number of data output from the integrated circuit elements and the total number of data input pins of the inspection apparatus (for example, the number of data input pins of the inspection apparatus). Is m = a × b and the output data of the integrated circuit element is a bit,
A maximum of b integrated circuit elements can be selected). 1
If only one or two integrated circuit elements are selected, not only does it take a long time to inspect all of the integrated circuit elements mounted on the inspection substrate, but also the efficiency of the inspection process decreases.

The problem of selecting such an integrated circuit device is described in Korean Patent Application No. 1997-1997 filed by the present applicant.
As disclosed in U.S. Pat. No. 32,280, it is particularly important when an integrated circuit device that operates in the merged data output mode and the standard operation mode is to be inspected using a single inspection substrate. In other words, instead of selecting a fixed number of integrated circuit elements in a standardized pattern, it is possible to arbitrarily select an integrated circuit element according to a user's selection by adding an optional property to a scan signal selection pattern. Should be.

The present invention has been made in view of such conventional problems, and has as its object to provide an inspection system capable of arbitrarily selecting a plurality of integrated circuit elements mounted on an inspection board. It is in.

Another object of the present invention is to provide an inspection system that shortens the inspection time of the burn-in inspection and increases the efficiency of the inspection process.

[0010]

According to a first aspect of the present invention, there is provided a burn-in inspection system, comprising: a plurality of integrated circuit elements mounted in a matrix; An inspection pattern section for generating a predetermined inspection pattern for function inspection of a plurality of integrated circuit elements mounted on a substrate, and a predetermined inspection pattern generated by the inspection pattern section are stored in the plurality of integrated circuit elements. A data inspecting unit that inspects output data from the plurality of integrated circuit elements to check for a defect in the plurality of integrated circuit elements, and detects an initial failure of the plurality of integrated circuit elements. An inspection system, comprising: a row direction selecting means for selecting a row-direction integrated circuit element mounted on the inspection board; and a column-direction integrated circuit element mounted on the inspection board. The choice of column selection means, at least is attached to an arbitrary position of the inspection on the substrate 2
The gist is to arbitrarily select more than two integrated circuit elements. Therefore, it is possible to arbitrarily select a plurality of integrated circuit elements mounted on the inspection board, shorten the inspection time of the burn-in inspection, and increase the efficiency of the inspection process.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in more detail with reference to the drawings.

FIG. 1 is a schematic block diagram of an inspection system according to the present invention.

The inspection system (10) is applied to a monitor burn-in inspection, and includes a chamber (34) for applying a thermal stress to an integrated circuit element to be inspected, and an electric signal applied to the integrated circuit element. And a plurality of circuit modules for measuring a signal output from the integrated circuit element.

The control unit (12) manages the entire inspection system, and the user operates the operation timing of the integrated circuit element to be inspected via the control unit (12), the chamber (3).
4) Set the temperature, voltage, etc., and specify the data pattern to control the addressing procedure. The control unit (1
The test pattern unit (test pattern generation unit) (14) controlled by 2) can generate and execute a standard memory test pattern, and can also generate and execute a test pattern defined by the user. In addition, the inspection pattern portion (1
4) generates and controls microprogram addresses transmitted to the data generator (28), the row address generator (16), and the column address generator (20). The data generator (28), the row address generator (16) and the column address generator (20) execute a microcode instruction specified by an address from the test pattern unit (14).

The row address generator (16) and the column address generator (20) generate address signals necessary for addressing an integrated circuit element (not shown) mounted on the inspection board (38). The generated row address signal and column address signal are input to the integrated circuit device via the row address driver (18) and the column address driver (20), respectively.

The selection signal generating section (24) is connected to the inspection board (3).
In order to select the integrated circuit element mounted in 8), a selection signal or a scan signal input through the selection signal driver (26) is generated. Output data output from the selected integrated circuit element is input via the data driver / receiver (32), and the data checker (30) checks the output data to determine whether the function of the integrated circuit element is normal. It can be checked whether it works.

The data generating section (28) executes the microinstruction of the inspection pattern section (14), for example, up to 32
Bit data is generated and transmitted to the integrated circuit device via the data driver / receiver (32). On the other hand, the output data output from the integrated circuit device is used by a data testing unit (30) for testing to check the operation function of the integrated circuit device.

The data inspection section (30) also performs an operation of storing data for an integrated circuit element determined to be defective as a result of the inspection. The bit and the address of the defective cell may be stored together. The data stored in the data inspection unit (30) is transmitted to the control unit (1).
It is transmitted to 2), analyzed and displayed on the screen.

The selection signal (scan signal) output from the selection signal driving section (26) is transmitted to the inspection pattern section (1).
An integrated circuit element having an arbitrary pattern according to the inspection pattern to be executed in 4) or the control of the user by the control unit (12) and arbitrarily mounted on an arbitrary position on the inspection board (38) is selected. can do.

In the chamber (34), a test board (3) on which a plurality of, for example, 128 integrated circuit elements are mounted.
8) is mounted, and the temperature inside the chamber (34) is controlled by a temperature controller (36) controlled by the controller (12).

For example, the temperature inside the chamber (34) is
According to the temperature graph shown in FIG. Referring to FIG. 2, in the section OA, the inside of the chamber (34) is maintained at a normal temperature, and the temperature rapidly rises to 83 ° C. in the section AB to apply thermal stress to the integrated circuit device. After the pressing, an electrical stress is applied to the integrated circuit device via the data driving / receiving unit (32) to accelerate the initial failure of the integrated circuit device. afterwards,
A function test is performed to confirm that the operation of the integrated circuit device is performed. In the next section BC, the temperature inside the chamber is set to 12
The temperature is raised to 5 ° C., and while the thermal stress is applied to the integrated circuit element, the electric stress is applied to the integrated circuit element, and the function test of the integrated circuit element is performed. And section CD
Then, the temperature is lowered to 83 ° C., and the pressurization of electric stress and the function test are performed.

FIG. 3 is a block circuit diagram of a selection signal generator (24) suitable for use in the inspection system according to the present invention. The selection signal generation unit (24) illustrated in FIG. 3 has an exemplary configuration for generating a selection signal that can arbitrarily select an integrated circuit element mounted on a test board.

The counter (40) is enabled (Enabl
e) It is driven in response to the signal E, is restored to the initial state by the reset signal R, and the output of the counter 40 is sequentially increased every time the increment signal I is inputted. The control signals E, I, R of the counter (40) are
It is supplied from the control unit (12) of the inspection system (10). The first buffer (41) has an address enable (Add
ress Enable) signal AE and the address signal A
_{0, A 1, ..., A} n an appropriate level, i.e., SRAM (Sta
tic RAM) (42) and outputs the converted level. Address signals _{A 0,} A 1 is input to the first buffer (41), ..., _{A n,} for example be supplied from the test pattern unit (14) or the control unit of the inspection system (10) (12) it can. The (n + 1) -bit output signal of the first buffer (41) is connected to the output of the counter (40) in a one-to-one manner, so that the SRAM (4)
The address signal input to 2) can be sequentially increased.

The SRAM (42) stores external data D ₀ , D ₁ ,
..., address signals _{D n A 0, A 1,} ..., it is stored as an element selection signal data to the memory cell specified by _{A n.} Data output from the SRAM (42) is supplied to the element selection signals S ₀ , S ₁ ,
..., it is supplied to the test substrate as S _n. The data buffer (45) includes a read / write signal R / W (Read / Write).
Controls the operation. During a write operation to the data buffer (45), the external data _{D 0,} D 1, ..., a _{D n} SR
The data is stored in the AM (42), and at the time of a read operation, data is diagnosed in order to store correct data at a specified address of the memory. The external data D ₀ , D ₁ ,..., D _n are:
It is supplied from the control unit (12) of the inspection system (10).

In order to store the element selection signal data in the SRAM (42), a write signal W is input to the data buffer (45), and the write signal W is also supplied to the SRAM (42).
Is input, but output enable OE (Output Enable)
Is not entered. On the other hand, the output of the counter (40) is in a high impedance state, and has no effect on the address signal input to the SRAM (42). When an address enable signal AE is supplied to the first buffer (41) for addressing the SRAM (42), the address signals A ₀ , A ₁ ,..., A input to the first buffer (41). _n selects a memory cell of the SRAM (42), and external data D ₀ ,
_{D 1,} ..., D _n is stored.

When the read signal R and the output enable signal OE are input to the SRAM (42), the data stored in the memory cell is output and the element selection signal S ₀ ,
S _1, ..., it is used as the _{S n.} At this time, the enable signal E is supplied to the counter (40) to
The address signal supplied to (42) is a counter (4
0). The address of the SRAM (42) increases every time the increase signal I is input to the counter (40), and the content of the data output signal of the SRAM (42) changes. Therefore, the SRAM (42)
According to the output data, an arbitrary integrated circuit element can be selected from a large number of integrated circuit elements mounted on the inspection board. After using the signals in all the states, the reset signal R returns the counter (40) to the initial state.

[0027] The element selection signals _{S 0,} S 1, ..., the pattern of _{S n,} the data _{D 0,} D 1 input to the data buffer (45), ... are input to the _{D n} and SRAM (42) The address signal and the data are determined by the control unit (12) of the inspection system.
The control unit (12) determines an address signal and data to be supplied to the SRAM (42) based on the test pattern generated and executed by the test pattern unit (14).

FIG. 4 is a schematic connection diagram showing a connection relationship between a plurality of integrated circuit elements mounted on an inspection board and scan signals for selecting the plurality of integrated circuit elements. FIG.
The test board shown in FIG.
As disclosed in U.S. Pat. No. 32280, an integrated circuit device that operates in a merged data output (Merged DQ: "MDQ") mode and a standard operation mode can be inspected using one substrate.

The inspection board (38) has, for example, 32 sockets, on which the integrated circuit element (70) to be inspected is mounted. The integrated circuit element (70) has, for example, eight input / output DQ terminals, and the input / output I / O terminals (62) of the inspection board (38).
Are 32 in total. The scan signals 0, 1, 16 to 19 enable only a specific one of the 32 integrated circuit elements, and are connected to the selection signal driver 26 of the inspection system. The address signal (66) is supplied to the row / column address driver (18, 22).
Supplies necessary address signals. I / O terminal (6
2) Since the power signal (65), the control signal (67), and the mode selection signal (68) are connected to the data driving / receiving unit (32) of the inspection system, the inspection system can generate signals necessary for the inspection. Is supplied to the integrated circuit element (70), and the output thereof can be read.

The power signal (65) and the address signal (6)
6), control signal (67) and mode selection signal (68)
Are all connected to the 32 integrated circuit elements (70), and the connection state is not shown for simplification of the drawing. The control signal (67) is, for example, an integrated circuit element (7
0) is a signal for controlling the operation of RAS (Row
Address Strobe), CAS (Column Address Strobe), W
E (Write Enable), OE (Output Enable), etc. are included. The mode selection signal (68) is a signal for selecting whether the integrated circuit element (70) should perform a normal standard operation or operate in the MDQ mode.

The selection of the MDQ mode is determined by the inspection system. When the integrated circuit device (70) shifts to the MDQ mode, a predetermined number of the merged data output terminals among the eight DQ terminals of the integrated circuit device, For example, 8-bit data is output simultaneously by 4 bits via two DQ terminals, DQ0 and DQ7. For example, 8M × 8 (64) where 1-bit data is output per 8M memory block
M) Row address (X0-X12) for DRAM device
And the most significant two bits (for example, Y11, Y11) of any one address signal in the column address (Y0-Y12).
If Y12) is a signal irrelevant to addressing, other address signals (for example, except for the upper two bits) (for example,
X0-X12, Y0-Y10) output data from four 8M memory blocks with the same DQ terminal (D
Q0 or DQ7). When data "1" is written to all memory cells of the integrated circuit element and output data is read from the memory cells, for example, when all four output data output via DQ0 are "1" Outputs normal data '1' to DQ0. However, if at least one of the four output data is '0', defective data '0' is also output to DQ0,
The integrated circuit element can be determined to be a defective element including a defective memory cell.

A column enable scan signal terminal (64a) for enabling the integrated circuit elements in each column among the 32 integrated circuit elements (70) arranged in a matrix.
Scan signal 0 enables the integrated circuit elements in the first and second columns and the third and fourth columns of the scan signal 1 in the row enable scan signal terminal (64b). On the other hand, scan signal 16, scan signal 17,
The scan signal 18 and the scan signal 19 are the first and fifth signals, respectively.
The data is input to the integrated circuit elements mounted on the rows, the second, sixth, third, seventh, fourth, and eighth rows. When scan signals 16 to 19 and scan signals 0 to 1 are all active,
Output data is output from the integrated circuit element located at the intersection. For example, among scan signals, scan signal 0
Is in the active state, and among the scan signals, the scan signal 16
Is active, the integrated circuit elements (1, 1) (1,
2) The output data can be read from the DQ terminals of (5, 1) and (5, 2).

I / O terminal (62) of inspection board (38)
Are composed of a total of 32 I / O terminals (6
2) and the DQ terminal of the integrated circuit element are connected to the wiring pattern (7
2) are electrically connected. The wiring pattern (72) is connected to the I / O terminals (6) in order without the output data output from the plurality of integrated circuit elements colliding with each other.
It must be designed to be supplied in 2). I /
O 0-7 are integrated circuit elements (1, 1), (2, 1),
(3,1), (4,1), (1,3), (2,3),
Linked to (3,3) and (4,3), I / O
8-15 are integrated circuit elements (1, 2), (2, 2),
(3, 2), (4, 2), (1, 4), (2, 4),
(3,4) and (4,4), and I / O
16-23 are integrated circuit elements (5, 1), (6, 1),
(7, 1), (8, 1), (5, 3), (6, 3),
(7,3) and (8,3), I / O
24-31 are (5, 2), (6, 2), (7, 2),
(8,2), (5,4), (6,4), (7,4) and (8,4).

When such an inspection board (38) is used, the inspection using the MDQ method and the inspection for the partially defective memory element can be performed together. Table 1 below shows the pattern of the element selection signal at this time.

[0035]

[Table 1] In Table 1, the element selection signal, scan signal 0, scan signal 1, and scan signals 16 to 19 are in an active state when the value is "1" and in an inactive state when the value is "0". . Therefore, for example, when the scan signal 0 is “1”
Then, the integrated circuit element to which the first and second column signals are connected is selected.

As described above, in the MDQ mode, 2-bit data is output from one integrated circuit element (70), and the I / O terminal (62) of the test board (38) has a total of 32 bits. As such, 16 integrated circuit elements can be selected at a time. Therefore, as is apparent from the element selection signal patterns 1 and 2, the scan signals 16 to 1
9 is an active state, and if the scan signal 0 and the scan signal 1 are alternately activated, output data output from a total of 32 integrated circuit elements is inspected, and any integrated circuit element has a defect. Get to know.

On the other hand, in the standard operation mode, 8-bit data is output from one integrated circuit element, and the test board (3
8) Since the I / O terminal (62) is 32 bits,
Four integrated circuit elements can be selected at a time. Therefore, Table 1
As shown in patterns 3 to 10 of FIG. 3, one of the scan signals 0 and 1 and the scan signals 16 to 19 is selectively activated to output signals from a total of 32 integrated circuit elements. Output data can be inspected. This makes it possible to know at which output terminal of the defective element the wrong data was output, so that utilization of the partially defective memory element (which can be used for a good module device configuration) can be studied.

As described above, the pattern of such an element selection signal is variously determined by the control unit of the inspection system appropriately determining the data and the address signal to be supplied to the selection signal generation unit according to the inspection pattern.

[0039]

As described above, according to the present invention,
Since the integration mounted on the inspection substrate can be arbitrarily selected according to the inspection pattern, the inspection time is shortened, and the efficiency of the inspection process is increased. In addition, a function test when the integrated circuit element operates in the merged data output mode and a function test when the integrated circuit element operates in the standard mode can be performed using one test board.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a burn-in inspection system according to the present invention.

FIG. 2 is a temperature graph for applying a thermal stress to an integrated circuit device in a burn-in test according to the present invention;

FIG. 3 is a block circuit diagram of a selection signal generator used in the inspection system according to the present invention.

FIG. 4 shows a plurality of integrated circuit elements mounted on an inspection board;
FIG. 3 is a schematic connection diagram illustrating a connection relationship with a scan signal for selecting an integrated circuit element.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Inspection system 12 Control part 14 Inspection pattern part 16 Row address generation part 18 Row address drive part 20 Column address generation part 22 Column address drive part 24 Selection signal generation part 26 Selection signal drive part 28 Data generation part 30 Data inspection part 32 Data Driving / receiving unit 34 Chamber 36 Temperature control unit 38 Inspection board

Continuation of the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G01R 31/26 G01R 31/28 H01L 21/66

Claims (1)

(57) [Claims] An inspection board on which a plurality of integrated circuit elements are mounted in a matrix, and an inspection pattern section for generating a predetermined inspection pattern for function inspection of the plurality of integrated circuit elements mounted on the inspection board And storing the predetermined test pattern generated by the test pattern unit in the plurality of integrated circuit elements, and inspecting output data from the plurality of integrated circuit elements to determine whether the plurality of integrated circuit elements are defective. A data inspection unit for confirming, comprising: a row direction selecting unit for selecting a row direction integrated circuit element mounted on the test board; By selecting a column-direction selecting means for selecting an integrated circuit element in a column direction mounted on the test board, at least two or more groups mounted at arbitrary positions on the test board are selected. Optionally inspection system capable of integrated circuit devices to be mounted on test board, characterized by arbitrarily selecting circuit elements.