JPH0829491A - Lsi testing device - Google Patents

Abstract

PURPOSE:To set data simultaneously to achieve a high speed by using an address signal for reading a pin select information from a pin select memory in which plural pieces of pin select information assumed are stored, and enabling selected pin registers simultaneously. CONSTITUTION:Pin select information selected through various tests is written in a pin select memory 2 prior to the test of an LSI (DUT) to be tested. In the test, address designation data is transferred via a data bus DB, and an address generation means 3 outputs an address signal to the memory 2. The memory 2 reads the pin select information corresponding to that address, and outputs an enable signal to a pin group selected from a pin register group 1. When data are transferred via the bus DB, the data are simultaneously set only in the register group 1 that has been enabled by the signal from the memory 2. Therefore, data setting time is shortened and a high speed can be achieved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI test device for testing a semiconductor device such as an LSI (large-scale integrated circuit, IC, memory IC), and more particularly, a controller (computer for controlling the test device. ) And a controlled circuit including an LSI (DUT) to be inspected.

[0002]

2. Description of the Related Art Semiconductor devices such as LSIs have made dramatic progress today, and various functions and configurations have become complicated. An LSI test device is used to perform such a semiconductor device test. LSI
The test apparatus applies a test signal to a desired pin of a controlled circuit including a DUT to be inspected through a driver, and according to the data output from the DUT and the applied test signal in advance. The quality of the DUT is judged by comparing the prepared expected value pattern with a comparator.

An LSI test apparatus having such a configuration is disclosed in, for example, Japanese Patent Laid-Open Nos. 60-130839 and 61-66973. Further, in such an LSI test apparatus, a typical interface circuit provided between a controller for controlling the test apparatus and individual pins of the DUT is provided in association with each pin of the DUT or controlled circuit, and is controlled. A pin register that holds information about the attributes to be processed, D
It is configured to include a driver that outputs a test signal to the UT.

The information regarding the attributes to be controlled held by the pin register includes, for example, information for controlling the state of a relay connected to each pin, information for indicating a reference level, information for indicating a pin operation mode, and precision analog. For example, connection of the measurement unit in the case of measurement. Conventionally, when data is supplied to these pin registers, each register connected to each pin is sequentially addressed and desired data is supplied. However,
Many of the pin registers receive the same data, and loading such data into each register requires a large number of repeated instructions and requires a long setup time. .

In order to solve such a problem, there is proposed one in which a participation register is provided in the interface circuit (Japanese Patent Laid-Open No. 59-230177). FIG. 5 is a configuration block diagram of the interface circuit shown here. This circuit comprises a data bus 130 for transferring data, an address bus 120 for transferring addresses, each having an individual address and a set of pins each connected to said data bus. A register 100 and an input terminal connected to the data bus and at least one output terminal connected to each of the pin registers 100, a plurality of for receiving data in parallel from the data bus 130. Of the pin register 100 for enabling the pin register, and each of the address bus 120, each of the pin registers 120 and the join register 150, of the pin register 100 to receive data from the data bus 130. Address decoder means 1 for enabling one or said participation registers It is configured to include a 0 and.

Here, the data to the participation register has an address of each of a plurality of pin registers which should receive the data in parallel from the data bus 130.

[0007]

The device having such a structure can eliminate the sequential address operation to the individual registers, and loads a group of registers in parallel for common data. Therefore, it has the feature that the setup time can be reduced. However, even in this device, it is necessary to set in the participation register 150 for each test, a pin group indicating which pin register participates in the test. Although setting this pin group is better than setting data for each pin, D
Assuming that the number of pins of the UT is 512 pins and the data bus 130 has a width of 16 bits, for example, the participation register 150 is set 32 times for each designation of one pin group. Is required.

Therefore, even with this improved prior art, there was a problem in reducing the set-up time. In the present invention, the time required for setting the pin group is made as short as possible.
It is an object of the present invention to provide an LSI test device capable of speeding up with the same set-up time even with 12 pins.

[0009]

SUMMARY OF THE INVENTION The present invention to achieve such an object is to provide an LSI test apparatus provided with a pin register which is provided in association with each pin of an LSI under test and holds data relating to an attribute to be controlled. In the above, a plurality of pin group select information assumed in advance is stored at different addresses, and a signal for enabling the pin register is read out from the pin select memory and an address based on the transferred data. An LSI test device, comprising: an address signal generating means for outputting a signal to a pin select memory, so that data can be simultaneously set in a pin register group designated according to an enable signal from the pin select memory. .

[0010]

The pin register is connected to the data bus, and the pin register group designated by the enable signal output from the pin select memory is set with the data regarding the attribute to be controlled, which is sent via the data bus. To be done. The address signal generating means is connected to the data bus and outputs an address signal for designating the address of the pin select memory based on the sent data.

In the pin select memory, pin group select information for designating a pin group selected according to the contents to be tested is stored in advance at each address, and the address designated by the address signal generating means is stored. The pin select information stored in is read out, and the selected pin register group is simultaneously enabled by these signals.

[0012]

An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a basic configuration conceptual diagram of an LSI test apparatus according to the present invention. In the figure, reference numeral 1 denotes a pin register, which is provided in association with each pin of an LSI under test (DUT) and holds data (parameters for each test) relating to attributes to be controlled.

Reference numeral 2 is a pin select memory, for example, RA
The M register is provided with a data width corresponding to the pin register, in which select information of a pin group used for each test is written in advance at each address. And when the address is specified,
The select information written at that address is read out, and the pin register group 1 is enabled based on this select information.

An address signal generating means 3 has a latch function of inputting the transferred data and outputting an address signal to the pin select memory 2 based on the data.
DB is a data bus, which is connected to the pin register 1, the pin select memory 2, and the address signal generating means 3. AB
Is an address bus, and an address signal is transferred when the pin select information is written in the pin select memory 2. The data bus DB and the address bus AB are connected to a controller (not shown).

The operation of the thus constructed apparatus will be described below. First, before the DUT is tested, the pin select memory 2 is written with pin select information selected for various tests. To write the select information, the addresses of the pin select memory 2 are sequentially specified via the address bus AB, and the select information of the pin group selected in various tests preliminarily assumed for each address is sent via the data bus DB. It is done by transferring and writing. For example, address 0 of the pin select memory 2 is select information for selecting the DUT address pin group, address 1 is receive information for selecting the DUT data pin group, and address 2 is the control pin group. In each test, select information for specifying a pin group to be used is written, such as select information to be selected.

Next, when a DUT test is performed, data designating the address in which the information of the pin group corresponding to the test is written is transferred to the data bus D.
Transfer via B. The address signal generating means 3 outputs an address signal to the pin select memory 2 based on the transferred data. Here, when the same pin group is continuously selected (when the test is repeated), the same address signal latched therein is continuously output from the address signal generating means 3. Becomes

When an address is designated, the pin select memory 2 reads the pin select information written in advance at the address and outputs an enable signal to the selected pin group of the pin register group 1. In the pin register group 1, when data is transferred via the data bus DB, the data is set all at once only to the pin register group enabled by the signal from the pin select memory 2. As a result, it is possible to shorten the time required to set the data in a large number of pin registers, and it is possible to increase the speed.

FIG. 2 is a block diagram showing the configuration of another embodiment of the present invention. In this embodiment, the pin select memory 2 is divided into eight pins, for example. Although only two circuits (circuit 1, circuit 2) are shown here, 64 circuits are actually prepared for 512 pins.

In this figure, 5 is a first decoder and 6
Is a second decoder, both of which are connected to the address bus AB, the lower address of the address signal is applied to the first decoder 5, and the upper address is applied to the second decoder 6. 51, 52, ... Are the first decoder 5
From the pin select memory 2 and outputs a signal for selecting the pin register 1. The signal from the second decoder 6 is applied to the enable terminal of the first decoder 5 and
It is applied to the corresponding pin select memory 2 and address signal generating means 3 as a signal for enabling them.

Reference numeral 7 denotes a third decoder which is uniquely provided in the entire circuit and which receives an address signal transferred through the address bus AB and which is a corresponding circuit (circuits 1 to 64).
The signal for selecting is output to the enable terminal of the second decoder 6. Reference numeral 8 denotes a controller for controlling the entire circuit, which is connected to an address bus AB and a data bus DB.

FIG. 3 is a conceptual diagram showing the select information of the pin group written in each pin select memory 2 in each circuit. Here, select information for selecting an address pin group is written in address 0 of each pin select memory 2. Select information for selecting the data pin group is written in the address 1, and select information for selecting the control pin group is written in the address 2.

FIG. 4 is a diagram showing a test flow before and during a test in the device constructed as described above.
Step 1 is a pre-test process, which is a process of writing the pin group select information to each pin select memory 2. The process after step 2 is a process for performing a test, and the process after step 2 is repeated during the test.

Step 2 is a procedure assuming the case of selecting an address pin group, and the address signal generating means 3 outputs an address signal for setting the address "0" to the pin select memory 2. In such a procedure, data for designating the address 0 of the pin select memory 2 is transferred from the controller 8 via the data bus DB, and which circuit is selected via the address bus AB (circuit 1, circuit 2 ... Selection) is sent. Address generating means 3 of the selected circuit
Outputs an address signal indicating address 0 to the pin select memory 2 based on the data and the address signal transferred from the controller 8 side. It should be noted that a plurality of circuits or all the circuits can be selected at the same time in selecting the circuits.

As a result, from the pin select memory 2,
The pin group select information (in this case, information designating the address pin group) previously written in the address 0 is read all at once. Here, the corresponding pin registers from which "1" has been read are enabled all at once. Subsequently, the controller 8 transfers the data to be output to the address pins via the data bus DB, and simultaneously writes the data to the enabled pin registers (registers corresponding to the address pins in this case) (step 3). ).

By such a procedure, it is possible to perform various tests such that the address pins are targeted and data is output to those pins. Then, for example, in the case of performing a test for the data pin group, an address signal for setting the address "1" is output to the pin select memory 2 (step 4). As a result, the pin group select information (in this case, information specifying the data pin group) previously written in the address 1 is simultaneously read from the pin select memory 2. here,
Corresponding pin registers for which "1" is read are all enabled.

Subsequently, the controller 8 transfers the data to be output to the data pins via the data bus DB, and simultaneously writes the data to the enabled pin registers (registers corresponding to the data pins in this case). (Step 5). By the procedure of steps 4 and 5 like this,
Various tests for data pins can be performed. Then, for example, when performing a test targeting the address pin group and the control pin group, first, an address signal for setting the address "0" is output to the pin select memory 2 (step 6). Next, the data to be output to the address pin is transferred via the data bus DB, and the data is written in the enabled pin registers all at once (step 7). Then, an address signal for setting the address "2" is output to the pin select memory 2 (step 8). Next, the data to be output to the address pin is transferred via the data bus DB, and the data is written in all enabled pin registers all at once (step 9). By the procedure of steps 6 to 9 as described above, a test for the address pin group and the control pin group can be performed.

In the above-described embodiment, if the select information for simultaneously selecting the address pin group and the control pin group is written in the pin select memory 2 beforehand, steps 6 to 6 in FIG. 9 can be two steps, such as steps 2 and 3.

[0028]

As described in detail above, the present invention provides
A pin select memory is prepared, target pin select information is written in advance in accordance with various tests, the select information is read from this pin select memory 2 at the time of the test, the corresponding pin register is enabled, and data is It was designed to write all at once. Therefore, even if the number of pins is increased, data can be written to the corresponding pin register group by designating the pin group once, and an LSI test apparatus capable of high-speed testing can be realized.

[Brief description of drawings]

FIG. 1 is a basic configuration conceptual diagram of an LSI test apparatus according to the present invention.

FIG. 2 is a configuration block diagram showing another embodiment of the present invention.

FIG. 3 is a conceptual diagram showing pin group select information written in each pin select memory 2 in each circuit.

FIG. 4 is a diagram showing a test flow before and during a test.

FIG. 5 is a configuration block diagram showing an example of a conventional device.

[Explanation of symbols]

 1 pin register 2 pin select memory 3 address signal generation means 51, 52, 53 ... AND gate circuit 5, 6, 7 decoder 8 controller DB data bus AB address bus

Claims (2)

[Claims] 1. An LSI test apparatus having a pin register, which is provided in association with each pin of an LSI under test and holds data relating to an attribute to be controlled, wherein select information of a pin group assumed in advance is assigned to a different address. A pin select memory for storing a plurality of signals from which a signal for enabling the pin register is read out, and an address signal generating means for outputting an address signal to the pin select memory based on the transferred data. An LSI test device characterized in that data can be simultaneously set in a pin register group designated according to an enable signal from the pin select memory. 2. An LSI test apparatus comprising a pin register which is provided in association with each pin of an LSI under test and holds data relating to an attribute to be controlled, wherein select information of a pin group assumed in advance is assigned to a different address. A plurality of pin select memories (2) in which a plurality of signals are stored and from which a signal for enabling the pin register is read out, and an address signal corresponding to an address signal based on the transferred data. And an AND gate circuit (51, 52, 53) for supplying the output signal to the corresponding pin register with the enable signal read from the pin select memory as one input.
...) and a decoder (5, 6, 7) that selects the plurality of pin select memories based on the transferred address signal and also selects the AND gate, and an enable signal from the pin select memory. An LSI characterized in that data can be simultaneously set in a designated pin register group according to the selection of an AND gate.
Test equipment.