JPS61196176A - Semiconductor ic tester - Google Patents

Abstract

PURPOSE:To contrive a higher speed testing, by attaching registers storing the subsequent test data respectively to a plurality of units so as to transfer the subsequent test data to the units simultaneously from the registers by a command from a central control section. CONSTITUTION:Registers R (R1, R2... and RN) are attached to respective units U (1,2...and N) so as to store test data into the registers previously before they enter the units U. Then, while an IC is being tested using test data for the first test items stored in the respective units U, test data for the second test items are stored into the respective registers R by a command of the CPU11. Then, upon the end of the testing for the fist test items, an ON command is provided to a gate register GR from the CPU11 to transfer test data for the second test items to the respective units U simultaneously from the respective registers R and thus, the speeding up of the test can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit testing device used for LSI testing and the like.

Recently, ICs have become highly integrated into LSI and VLSI.
As testing has become more complex, test systems are now being used that use computers to input test patterns and automatically perform tests.

There has been a demand for such test equipment to be as fast as possible in testing, and this is natural in order to improve throughput.

[Prior Art] FIG. 2 shows a schematic block diagram of a conventional test device.As is well known, a computer 10 is connected to a central control unit (CP
U) 11 and a storage section (memory) 12, and a large number of units 1. Unit 2゜Unit 3...Connected to unit N.

For example, unit 1 is a voltage source.

Unit 2 is the voltage level of the driver, unit 3 is the tamming generator, etc. The IC test equipment is composed of a combination of these units, and the test pattern is input to these units to perform the IC test. It will be done.

A test pattern is a large number of test items in a fixed order, such as a DC test or a functional test. For example, in a functional test, if you measure the access time at vcc = 4.5 V,
Next, several dozen test items are patterned, such as measuring the access time at VCC=5.5V. These are stored in designated memory addresses of the computer, and are transferred to each unit one after another according to instructions from the CPU.

[Problems to be Solved by the Invention] By the way, in such a test device, the CPU 11 issues a start command, and when one test item is completed,
Since all you have to do is specify the address of the next test item, the CPU
has relatively more time.

The present invention aims to improve this point and further speed up the testing apparatus.

[Means for solving the problem] The problem is that each of a plurality of units is provided with a register storing the next test data, and the next test data is transferred from the register to the unit according to a command from the central control unit. This problem can be solved by a semiconductor integrated circuit testing device that allows data to be transferred all at once.

[Operation] In other words, the present invention utilizes a relatively spare CPU to send the data necessary for the next test item to the registers in advance, and then sends the data from each register to the unit at once according to a command from the CPU. This is what you are trying to transfer. Then the CPU
can reduce the time it takes to set the next command.

[Example] An embodiment will be explained below with reference to FIG.

R1, R2, R3...RN are registers related to the present invention, and other symbols are the same parts as in FIG. 2 with the same symbols.

As shown, each unit is associated with a respective register, and test data is pre-stored in the register before entering the unit. Then, while the IC is being tested using the test data for the first test item stored in each unit, the test data for the next second test item is stored in each register under the command of the CPU. .

Subsequently, when the first test item is completed, the test data of the second test item stored in each register is turned on from the CPU to the gate register GR, and the test data of the second test item stored in each register is transmitted from each register. Test data is transferred to each unit simultaneously.

In this way, compared to the conventional method, the time required for the CPU to set the conditions for the next test item can be saved, and the speed can be increased accordingly.

In other words, the present invention aims to speed up testing by incorporating hardware registers into the program processing of a testing device.

[Effects of the Invention] As is clear from the above description of the embodiment, according to the present invention, IC testing can be further speeded up and throughput can be improved.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of a semiconductor integrated circuit testing device according to the present invention, and FIG. 2 is a schematic block diagram of a conventional semiconductor integrated circuit testing device. In the figure, 1.2.3...N is a unit, 10 is a computer, 11 is a central control unit (CPU), 12 is a storage unit (memory), 13 is an interface, R1, R2, R3...RN is a register , GR indicate gate registers.

Claims (1)

[Claims] A test device in which a plurality of units and a central control unit are connected through an interface, each of the units is provided with a register storing the next test data; While the test is being conducted, second test data is stored in the register according to a command from the central control unit;
A semiconductor integrated circuit characterized in that when the test using the first test data is completed, the second test data is transferred from the register to the unit all at once according to a command from a central control section. Test equipment.