JPS628031B2 - - Google Patents

Info

Publication number
JPS628031B2
JPS628031B2 JP56168432A JP16843281A JPS628031B2 JP S628031 B2 JPS628031 B2 JP S628031B2 JP 56168432 A JP56168432 A JP 56168432A JP 16843281 A JP16843281 A JP 16843281A JP S628031 B2 JPS628031 B2 JP S628031B2
Authority
JP
Japan
Prior art keywords
metal
film
barrier metal
wiring pattern
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56168432A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5868949A (ja
Inventor
Kenzo Hatada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP56168432A priority Critical patent/JPS5868949A/ja
Publication of JPS5868949A publication Critical patent/JPS5868949A/ja
Publication of JPS628031B2 publication Critical patent/JPS628031B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP56168432A 1981-10-20 1981-10-20 半導体装置の製造方法 Granted JPS5868949A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56168432A JPS5868949A (ja) 1981-10-20 1981-10-20 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56168432A JPS5868949A (ja) 1981-10-20 1981-10-20 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS5868949A JPS5868949A (ja) 1983-04-25
JPS628031B2 true JPS628031B2 (en, 2012) 1987-02-20

Family

ID=15868003

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56168432A Granted JPS5868949A (ja) 1981-10-20 1981-10-20 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS5868949A (en, 2012)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS513194A (ja) * 1974-06-24 1976-01-12 Fuji Electric Co Ltd Hinanjudohokojidosetsuteihoho
JPS6050334B2 (ja) * 1978-11-28 1985-11-08 松下電器産業株式会社 半導体装置

Also Published As

Publication number Publication date
JPS5868949A (ja) 1983-04-25

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