JPS6265866U - - Google Patents
Info
- Publication number
- JPS6265866U JPS6265866U JP15753185U JP15753185U JPS6265866U JP S6265866 U JPS6265866 U JP S6265866U JP 15753185 U JP15753185 U JP 15753185U JP 15753185 U JP15753185 U JP 15753185U JP S6265866 U JPS6265866 U JP S6265866U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit element
- wiring pattern
- view
- pattern surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000853 adhesive Substances 0.000 claims description 2
- 230000001070 adhesive effect Effects 0.000 claims description 2
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
Description
第１図は本考案集積回路素子の実装例を示す要
部縦断面図。第２図ａ，ｂ，ｃは本考案に使用す
るＬＳＩチツプをウエハーから分離して構成する
様子を示す手順図。ａ図は、ウエハーに切込みを
入れた状態の側面図。ｂ図は、上記ａ図に絶縁コ
ートを施した状態の側面図。ｃ図は、上記ｂ図を
切込み溝から切断しチツプ化した状態の側面図。
第３図は、従来のＬＳＩチツプの実装例を示す部
分断面図。第４図は、第３図によつて生じた欠陥
部を示す拡大側面図。
１…ＬＳＩチツプ、２…斜面部、３…絶縁コー
ト、４…異方性導電接着コート、５…配線パター
ン。
FIG. 1 is a vertical cross-sectional view of essential parts showing an example of mounting the integrated circuit device of the present invention. FIGS. 2a, 2b, and 2c are procedural diagrams showing how the LSI chips used in the present invention are separated from the wafer. Figure a is a side view of the wafer with cuts made. Figure b is a side view of the figure a above with an insulation coat applied. Fig. c is a side view of the above-mentioned Fig. b cut into chips by cutting from the cut groove.
FIG. 3 is a partial cross-sectional view showing an example of mounting a conventional LSI chip. FIG. 4 is an enlarged side view showing the defect caused by FIG. 3. DESCRIPTION OF SYMBOLS 1...LSI chip, 2...Slope part, 3...Insulating coat, 4...Anisotropic conductive adhesive coat, 5...Wiring pattern.
Claims (1)
面と対面する面の稜線部を面取りして斜面部を形
成し、該集積回路素子を、プリント基盤上の該配
線パターン面に絶縁コートを介して異方性導電接
着シートにより実装することを特徴とする集積回
路素子の装着構造。 The ridgeline portion of the surface facing the wiring pattern surface of the chip constituting the integrated circuit element is chamfered to form a sloped surface, and the integrated circuit element is anisotropically attached to the wiring pattern surface on the printed circuit board via an insulating coat. A mounting structure for an integrated circuit element, characterized in that it is mounted using a conductive adhesive sheet.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15753185U JPS6265866U (en) | 1985-10-14 | 1985-10-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15753185U JPS6265866U (en) | 1985-10-14 | 1985-10-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6265866U true JPS6265866U (en) | 1987-04-23 |
Family
ID=31080165
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15753185U Pending JPS6265866U (en) | 1985-10-14 | 1985-10-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6265866U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2016132548A1 (en) * | 2015-02-20 | 2017-11-30 | オリンパス株式会社 | Therapeutic energy application structure and medical treatment apparatus |
-
1985
- 1985-10-14 JP JP15753185U patent/JPS6265866U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2016132548A1 (en) * | 2015-02-20 | 2017-11-30 | オリンパス株式会社 | Therapeutic energy application structure and medical treatment apparatus |