JPS6265363A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To decrease the collector resistance and to improve the operating speed, by providing a lateral bipolar transistor within a well region while providing a vertical bipolar transistor such that a well region serves as a collector region. CONSTITUTION:A lateral bipolar transistor is composed of a P-type semiconductor region 5 for providing a base region, an N<+> type semiconductor region 6 for providing an emitter region and an N<+> type semiconductor region 7 for providing a collector region. The impurity concentrations of the emitter region 6 and of the collector region 7 are equivalent to that of the source/drain regions of an N-channel-type MISFET. The emitter region 6 is isolated from the collector region 7 by means of an annular polycrystalline silicon layer 8, while the collector region 7 surrounds the emitter region 6. The polycrystalline silicon layer 8 is formed to have as small a width as possible, so that a distance smaller than the width is defined between the emitter region 6 and the collector region 7. By constructing the collector region 7 in this manner, the collector resistance can be decreased.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor integrated circuit device, and in particular, to a technique that is effective when applied to a semiconductor integrated circuit device equipped with an MI S FET and a bipolar transistor. It is.

[Background technology] A technique for forming a MISFET and a bipolar transistor on one semiconductor substrate is disclosed in, for example, Japanese Patent Laid-Open No. 58-273.
It is described in Publication No. 57. The technique disclosed in this publication attempts to form a driving transistor at the output terminal of a static RAM formed of MISFETs using a bipolar transistor with a large driving ability.

According to the studies of the present inventors, the collector of the bipolar transistor in the above technique is made of a semiconductor substrate, and is not very practical.

On the other hand, considering increasing the speed of static RAM, it is considered necessary to use bipolar transistors also in the internal circuit. According to the inventor's study, when an internal circuit, such as a sense amplifier, is configured with bipolar transistors, a high amplification factor (high hF=:
), that is, a particle (vertical) transistor is suitable. On the other hand, as the bipolar transistors constituting the output buffer etc., according to studies by the present inventors, transistors with small collector resistance, that is, lateral transistors, are suitable in order to secure the output level. However, M on one semiconductor substrate
If the ISFET and two types of bipolar transistors were formed in separate processes, the manufacturing process of the semiconductor integrated circuit device would become extremely complicated.

[Object of the Invention] An object of the present invention is to provide a technique that can form a MISFET and two bipolar transistors without complicating the process.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

That is, the lateral bipolar transistor is provided in a well region, and the particle bipolar transistor is provided so that the well region becomes the collector region.

Hereinafter, the configuration of the present invention will be explained along with examples.

In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

Embodiment I FIG. 1 is a plan view of the lateral bipolar transistor of this embodiment, and FIG. 2 is a sectional view taken along the line A--A in FIG. 1. Note that in FIG. 1, insulating films other than the field insulating film are not shown in order to make the configuration easier to see.

In FIGS. 1 and 2, reference numeral 1 denotes a P-type semiconductor substrate, and an n-type well region 2 is provided on the surface portion. 3 is a field insulating film, and 4 is a P+ type channel stopper region.

The lateral bipolar transistor is composed of a p-type semiconductor region 5 as a base region, an n+-type semiconductor region 6 as an emitter region, and an n+-type semiconductor region 7 as a collector region. Note that, hereinafter, the p-type semiconductor region 5 will be simply referred to as a base region. Similarly, the n + -type semiconductor region 6 is called an emitter region, and the n + -type semiconductor region 7 is called a collector region. The base region 5 is provided on the surface of the well region 2, and its periphery is defined by the field insulating film 3. The depth from the surface to the bottom of the base region 5 is approximately 0.5 [μm]. The impurity concentration is higher than that of the well region 2 and lower than that of the emitter region 6 and the collector region 7. The emitter region 6 is provided on the surface of the base region 5, and the depth from the surface to the lower part is the emitter region 6 and the N-type well region 2.
Determine the depth so that it can withstand a sufficient voltage, for example, 10 [V] or more. Like the emitter region 6, the collector region 7 is provided on the surface of the base region 5. The impurity concentrations of the emitter region 6 and collector region 7 are n-channel type M
This is comparable to the source and drain regions of an ISFET. Emitter region 6 and collector region 7 are separated by a ring-shaped polycrystalline silicon layer 8, as shown in FIGS. 1 and 2. This is because the polycrystalline silicon layer 8 was used as a mask for impurity introduction. That is, the emitter region 6 is provided on the surface of the semiconductor substrate 1 inside the ring-shaped polycrystalline silicon layer 8, and the collector region 7 is provided on the surface of the semiconductor substrate 1 outside the polycrystalline silicon layer 8. Therefore, the collector region 7 is provided so as to surround the emitter region 6. This is to increase the opposing area of emitter region 6 and collector region 7 to reduce collector resistance. Note that emitter region 6 is not provided in a part of the surface of semiconductor substrate 1 surrounded by polycrystalline silicon layer 8 . This is to connect a conductive layer 9, which will be described later, to the base region 5 by exposing a portion of the base region 5 on the surface of the semiconductor substrate 1. The distance between the emitter region 6 and the collector region 7 is defined by the width of the polycrystalline silicon layer 8 (the gate length in the MI S FET). Therefore, if the width of the polycrystalline silicon layer 8 is formed using the minimum processing dimension in the manufacturing process,
The distance between emitter region 6 and collector region 7 is less than that. This is because impurities such as phosphorus (P) and arsenic (As) for forming the emitter region 6 and collector region 7 are isotropically diffused.

Further, as described above, by forming the collector region 7, the collector resistance is reduced.

In this way, the bipolar transistor with reduced collector resistance is effective for the output buffer 7 and the like. This is because when the resistance of the semiconductor element constituting the output buffer circuit is large, the signal level decreases, and the output level of the semiconductor integrated circuit device decreases.

What are the surfaces of polycrystalline silicon layer 8 and semiconductor substrate 1?

It is insulated with a thin insulating film 10. Further, the polycrystalline silicon layer 8 is covered with an insulating film 11 made of phosphosilicate glass (PSG) or the like. Further, a conductive layer 9 made of an aluminum layer is applied to the base region 5 through the contact hole 12. It is connected to the emitter region 6 or the collector region 7.

Note that the lateral bipolar transistor is C-M
It can be formed in almost the same process as I5FET, but
That will be explained later.

Next, a description will be given of a particle bipolar transistor that is effective when applied to a circuit that requires a large current amplification factor, such as a sense amplifier.

FIG. 3 is a plan view of the particle bipolar transistor of this embodiment, and FIG. 4 is a sectional view taken along the line AA in FIG. 3. Note that insulating films other than the field insulating film 3 are not shown in FIG. 3 in order to make the structure easier to see.

The base region 5 is provided on the surface of the well region 2 inside the field insulating film 3 formed in a ring shape. Emitter region 6 is provided on a part of the surface of base region 5 . Collector region 7 is provided on the surface of well region 2 so as to surround base region 5 . The collector region 7 and the base region 5 are electrically separated by the ring-shaped field insulating film 3. Base region 5, emitter region 6
The impurity concentration of the collector region 7 is the same as that of the lateral bipolar transistor. In addition.

In reality, the collector region 7 is a high impurity concentration region for connecting the collector electrode 9, and the collector consists of the well region 2.

Bipolar transistors have a large current amplification factor.

It is effective when applied to circuits that amplify minute signals such as sense amplifiers. By increasing the output of the sense amplifier, the difference between, for example, 1'', it O, information and the reference level for determining that information increases.

Note that the P+ type semiconductor region 5A provided in the base region 5 is
The impurity concentration is higher than that of the surrounding base region 5.

This is to establish ohmic contact with the base electrode 9. This area 5A is a P-channel MISF, which will be described later.
It can be formed by an ET source and drain forming process.

Next, the lateral bipolar transistor shown in FIGS. 1 and 2 and the particle bipolar transistor shown in FIGS. 3 and 4 are C (complementary type)-MI
It will be explained that it can be formed in substantially the same process as SFET.

First, the structure of the C-MI 5FET will be briefly explained. FIG. 5 is a plan view of the C-MI 5FET, and FIG. 6 is a sectional view taken along the line A--A in FIG. In addition, the fifth
Insulating films other than the field insulating film 3 are not shown in the figure to make the configuration easier to understand.

In FIGS. 5 and 6, the n-channel MISFET
is an n+ type semiconductor region 13 which becomes a source and drain region.
, a gate insulating film 14 and a gate electrode 15. The P channel type MISFET is composed of a P' type semiconductor region 16 serving as a source and drain region, a gate insulating film 14, and a gate electrode 15. The gate electrode 15 is P
It is integrated with a channel type MISFET and an n-channel type MISFET. A conductive layer 9 made of an aluminum layer is connected to the gate electrode 15, the P' type semiconductor region 16, and the rl+ type semiconductor region 13 through the connection hole 12. The input to the C-MI 5FET is through the conductive layer 9 connected to the gate electrode 15. The output is taken out from the conductive layer 9 connected to the P' type semiconductor region 16 and the N' type semiconductor region 13, which are train regions. The conductive layer 9, which is connected to the P1 type half region 16 which is the source region, is connected to the electric potential Vcc, for example, 5 [V].

The conductive layer 9 connected to the n-type semiconductor region 13, which is a source region, is connected to a ground potential Vss, for example, 0[V], which is a reference level for electrical operation of a semiconductor integrated circuit device.

On the other hand, a conductive layer 9 is also connected to the well region 2 through a connection hole 12, which is connected to a power supply of Vcc. An n+ type semiconductor region 17 is provided on the surface of the well region 2 to which the conductive layer 9 is connected.

Next, the lateral bipolar transistors shown in FIGS. 1 and 2 and the particle bipolar transistors shown in FIGS. 3 and 4 are connected to the C-MI shown in FIGS. 5 and 6.
It will be explained that it can be formed in almost the same process as SFET.

Note that the manufacturing process will be explained using FIGS. 1 to 6.

First, a well region 2 is formed by a well-known technique, and then a field insulating film 3 and a p-type channel stopper region 4 are formed. Next, base regions 5 of the lateral bipolar transistor and the particle bipolar transistor are formed by ion implantation. A resist is used as a mask for ion implantation. The mask is formed over the entire region other than the region where the bipolar transistor is provided. Also,
The mask forms a region where the base region 5 of the well region 2 of the particle bipolar transistor is not provided. The ion implantation is used in SRAM, DRAM, etc. Ion implantation can be used to form a P-type semiconductor region for alpha radiation protection. That is, the P layer provided below the n+ type semiconductor region of the MISFET that constitutes the memory cell or further below the n+ type semiconductor region under the conductive plate that constitutes the capacitive element.
Ion implantation can be used to form a type semiconductor region.

After the ion implantation, a gate insulating film 14 is formed by oxidizing the surface of the semiconductor substrate 1. This gate insulating film 1
In the step of forming 4, a thin insulating film lO is formed on the surfaces of the lateral bipolar transistor and the particle bipolar transistor.

Next, a gate electrode 15 of the MI S FET is formed using a polycrystalline silicon layer obtained by CVD or the like. An n-type impurity such as phosphorus (P) or arsenic (A s ) is introduced into the gate electrode 15 made of a polycrystalline silicon layer.

This is to reduce the resistance value.

In the step of forming gate electrode 15, polycrystalline silicon layer 8 is formed to separate emitter region 6 and collector region 7 of the lateral bipolar transistor. Note that a high melting point metal layer such as molybdenum (Mo), tungsten (W), titanium (Ti), tantalum (Ta), etc. may be used for the gate electrode 15. Further, a silicide layer of the above-mentioned high melting point metal may be used. Furthermore, the high melting point metal layer or silicide layer may be provided on top of the polycrystalline silicon layer. When the gate electrode 15 is configured as described above, the polycrystalline silicon layer 8 of the lateral bibolar transistor is also made of a high melting point metal or silicide like the gate electrode 15, or alternatively, a high melting point metal is formed on the polycrystalline silicon. A two-layer structure including metal or silicide is formed. After forming the gate electrode 15 and the polycrystalline silicon layer 8, the n++ semiconductor region 13 of the n-channel MISFET is formed by ion implantation. Using this ion implantation, the emitter region 6 of a lateral bipolar transistor and a particle bipolar transistor is
and a collector region 7 are formed. As the impurity, an n-type impurity such as phosphorus or arsenic is used. A resist is used as a mask for ion implantation. The mask is formed so as to cover at least the area on the semiconductor substrate 1 other than the P-channel type MI S FET, the emitter region 6, and the collector region 7. Therefore, a part of the base region 5 appearing on the surface of the semiconductor substrate l of the lateral bipolar transistor shown in FIG. 1 is covered with a mask. Similarly, a part of the base region 5 appearing on the surface of the semiconductor substrate l of the particle bipolar transistor shown in FIG. 3 is covered with a mask. After ion implantation, the resist mask is removed.

Next, p++ semiconductor region 1 of P channel type MISFET
6 is formed by ion implantation. As impurities,
For example, boron (B) is used. A resist is used as a mask, and it is formed over the entire area of the semiconductor substrate 1 other than the area where the P-channel MISFET is provided. At this time, at the same time, P of the particle bipolar transistor shown in FIG.
A type base electrode connection region 5A is formed. After the ion implantation, the mask is removed and the insulating film 11 is formed using a well-known technique.
, the connection hole 12 and the conductive layer 9 are sequentially formed.

As can be understood from the above description, the lateral bipolar transistor and the particle bipolar transistor of this embodiment can be formed in substantially the same process as the C-MI S FET.

[Embodiment 2] FIG. 7 is a plan view of a partial bipolar transistor according to Embodiment 2 of the present invention, and FIG. 8 is a sectional view taken along the line AA in FIG. 7.

In Example 2, an n++ semiconductor region 1 is provided under the base region 5.
8, the collector resistance of the bipolar transistor is reduced. Note that in FIG. 7, insulating films other than the field insulating film 3 are not shown in order to make the structure easier to see.

As shown in FIGS. 7 and 8, the base region 5 is provided on the surface of the well region 2 and is surrounded by a field insulating film 3. As shown in FIG. An emitter region 6 is provided on a part of the surface of the base region 5. Collector region 7 is provided on the surface of well region 2 .

Collector region 7 is also separated from base region 5 by field insulating film 3 . In this embodiment, the well region 2 is used as a part of the collector region 7, but in the following description, the well region 2 and the collector region 7 will be explained separately.

A 0+ type half region 18 is provided from the lower part of the base region 5 to the lower part of the collector region 7. This n-type semiconductor region 18 has a higher impurity concentration than the well region 2, and therefore has a lower resistance than the well region 2. Therefore, the collector current flowing in the well region 2 mainly flows in the n-type semiconductor region 18. That is, by providing the n-type semiconductor region 18, the decrease in output level due to collector resistance can be reduced.

A thin insulating film 1 is provided in the emitter region 6 and the collector region 7.
The polycrystalline silicon layer 8 is formed through the opening 19 formed by removing 0.
is connected. A conductive layer 9 made of an aluminum layer is connected to one end of this polycrystalline silicon layer 8 through a connection hole 12. Similarly, a layer 9 is connected to the base region 5 through a contact hole 12 and a conductor'.

Next, a method of manufacturing the bipolar transistor of this embodiment will be explained.

First, the well region 2 is formed using a well-known technique. Next, a type II conductor region 18 is formed by ion implantation. Phosphorus or arsenic is used as an impurity. The ion implantation energy is set so that the peak value of the TI type semiconductor region 18 is deeper than the base region 5. Specifically, it is set to about 800 [KeV]. Next, a field insulating film 3 and a channel stopper region 4 are sequentially formed using a well-known technique. Next, a thin insulating film 10 is formed by oxidizing the surface of the semiconductor substrate 1 exposed through the field insulating film 3. The process of forming this thin insulating film 10 is the process of forming the gate insulating film 14 of the MISFET. Next, base region 5 is formed by ion implantation. As this ion implantation step, as described in Example (2), the ion implantation step for forming a p-type semiconductor region for alpha ray countermeasures can be used. During the ion implantation, the well region 2 which becomes the base region 5 is
The surface of the semiconductor substrate 1 other than the surface thereof is covered with a resist 1-. That is, the surface of the well region 2, which will become the collector region 7, is covered with resist. It is not necessary to provide a resist on the surface of the well region 2 which will become the emitter region 6, because the emitter region 6 is formed by converting a part of the base region 5 to n-type.

After ion implantation, the resist is removed. next.

The thin insulating film 10 on the base region 5 which is to become the emitter region 6 and the thin insulating film 10 on the well region 2 which is to become the collector region 7 are removed to form an opening 19. Next, C
A polycrystalline silicon layer 8 is formed over the entire surface of the semiconductor substrate 1 by a VD method or the like. The step of forming this polycrystalline silicon layer 8 is the step of forming the gate electrode 15 of 1Ml5F' ET.

The polycrystalline silicon layer 8 is made to contain n-type impurities such as phosphorus and arsenic by thermal diffusion or the like. Through this thermal diffusion process, impurities are introduced into the semiconductor substrate 1 from the portion of the polycrystalline silicon layer 8 that is attached to the semiconductor substrate 1. That is, emitter region 6 and collector region 7 are formed by diffusion of impurities from polycrystalline silicon layer 8 . After the thermal diffusion, unnecessary portions of the polycrystalline silicon layer 8 formed over the entire area on the semiconductor substrate 1 are selectively removed. Next, the insulating film 11. A contact hole 12 and a conductive layer 9 are formed.

Note that the base region 5. As explained in Example I, the emitter region 6 and collector region 7 are of P-channel type M
It can be formed in the process of forming the source and drain regions of an I S FET or an n-channel MISFET.

[Effects] According to the new technology disclosed by the present application, the following effects can be obtained.

(1) By providing the collector region in the base region close to the emitter region, the collector current flows through the surface of the base region, which is the shortest direct radiation between the collector region and the base region, resulting in a lateral bipolar structure with low collector resistance. A transistor can be configured.

(2) The emitter region and collector region are formed by ion implantation using a conductive layer such as a polycrystalline silicon layer formed with minimum processing dimensions as a mask, so that impurities that will become the emitter region and collector region are absorbed into the conductive layer. Since the emitter region and the collector region can be placed close to each other within the minimum processing size, the emitter region and the collector region can be placed close to each other within the minimum processing size.

(3) By configuring a decoder, buffer, etc. using the lateral bipolar transistor, signal delay caused by the collector resistance is reduced, so that the electrical operating speed of the semiconductor integrated circuit device can be improved.

(4) providing a base region on a part of the surface of the well region;
By forming an emitter region within this base region and providing a collector region on the surface of the well region where the base region is not provided, the collector current flows into the bottom surface, which has a larger area than the side surfaces of the emitter region. A particle bipolar transistor that can flow a collector current, that is, can obtain a large current amplification factor, can be configured.

(5) By configuring a circuit that requires a large current amplification factor, such as a sense amplifier, using the above-mentioned particle bipolar transistor, it is possible to increase the potential difference between the signal connection level and the electric signal, thereby increasing the reliability of information readout. can be improved.

(6) Since the lateral bipolar transistor or the particle bipolar transistor can be formed in substantially the same process as the C-MISFET, the manufacturing process of the semiconductor integrated circuit device can be shortened.

(7) providing a base region on a part of the surface of the well region;
In a partical bipolar transistor configured by providing an emitter region within the base region and providing a collector region on the surface of the well region where the base region is not provided, the well region extends from the bottom of the base region to the bottom of the collector region. By providing a highly doped semiconductor region having the same conductivity type as the semiconductor region, a collector current flows through the highly doped semiconductor region, thereby reducing collector resistance.

The present invention has been specifically explained above using examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

[Brief explanation of drawings]

1 is a plan view of the lateral bipolar transistor of Example I, FIG. 2 is a sectional view taken along the line A-A in FIG. 1, FIG. 3 is a plan view of the particulate bipolar transistor of Example I, The figure is a sectional view taken along the line AA in FIG. 3. FIG. 5 is a plan view of the C-MISFET, and FIG. 6 is a sectional view taken along the line A--A in FIG. FIG. 7 is a plan view of the bipolar transistor of Example H, and FIG. 8 is a sectional view taken along the line AA in FIG. 7. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Well, 3... Field insulating film, 4... Channel stopper region, 5.5A
, 6.7.13.16.17.18... semiconductor region,
8.9.12.15... Conductive layer, 10.11.14.
Insulating film, 12.19... connection hole. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] 1. First and second bipolar transistors formed in a well region of a second conductivity type provided in a semiconductor substrate of a first conductivity type, the emitter and collector of the first bipolar transistor and a base region are formed within a well region, and a collector region of the second bipolar transistor is comprised of the well region. 2. The semiconductor integrated circuit device according to claim 1, wherein the collector region of the second bipolar transistor comprises a well region and the second semiconductor region provided on the surface of the well region. 3. The semiconductor integrated circuit device according to claim 1, wherein the first bipolar transistor is a lateral transistor, and the second bipolar transistor is a vertical transistor. 4. The semiconductor integrated circuit device according to claim 1, wherein the first bipolar transistor and the second bipolar transistor are formed using a process of forming a complementary MISFET. 5. The semiconductor integrated circuit according to claim 1, wherein the collector resistance of the first bipolar transistor is smaller than that of the second bipolar transistor, and the current amplification factor of the second bipolar transistor is larger than that of the first bipolar transistor. Device. 6. The semiconductor integrated circuit device according to claim 1, wherein the first bipolar transistor constitutes a circuit that requires a small collector resistance, and the second bipolar transistor constitutes a circuit portion that requires a high amplification factor. . 7. The semiconductor integrated circuit device according to claim 1, wherein a fourth semiconductor region having the same conductivity type as the well region and having a higher impurity concentration than the well region is provided in the well region below the bipolar transistor.