JPS60124872A - Vertical type mos field-effect transistor - Google Patents

Abstract

PURPOSE:To reduce capacitance between a wire bonding region for a gate electrode and a drain up to a high frequency region by forming the wire bonding region for the gate electrode and a wiring section for the gate electrode on a shielding electrode, which consists of the same material as a gate and is connected to a source electrode on a substrate surface. CONSTITUTION:A shielding electrode 14 composed of the same material as a gate electrode is formed between a substrate 1 and a wire bonding region 10 for the gate electrode through an oxide film, the shielding electrode 14 is kept at the same potential as a source electrode by a contact 15 for the shielding electrode, and capacitance Cgd between a gate and a drain is reduced. Since the shielding electrode 14 consists of the same material as the gate electrode 4 and the resistance of the same material as the gate electrode 4 and the resistance of the material is lower than conventional materials by one figure or more, the potential of the shielding electrode 14 can be made positively the same as the potential of the source electrode, and the potential of the shielding electrode 14 positioned under the bonding region 10 for the gate electrode hardly floats.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a so-called vertical MO8 field effect transistor having a source and a gate electrode on the surface of a semiconductor substrate and a drain on the back surface of the semiconductor substrate.

Conventional configuration and its problems Vertical MO8 field effect transistors are
H2, etc.), and in order to obtain a high gain, it is necessary to sufficiently reduce the feedback capacitance between the input and output. When a vertical MO3 field effect transistor is used with a common source, the feedback capacitance is the gate-drain capacitance (Cqd). Cqd
can be divided into the capacitance of the active region of the transistor itself and the bonding pad capacitance of the gate electrode wire bonding region on the substrate surface. The ratio of this bonding pad capacitance to the entire Cqd may reach 50 or more, although it depends on the area of the active region of the transistor. Therefore, in order to reduce cga and obtain high gain by reducing this bonding pad capacitance, it is necessary to increase the thickness of the insulating film under the gate electrode wire bonding area, or to connect the source under the gate electrode wire bonding area. A three-part method has been used in which a diffusion layer of the opposite conductivity type is formed on the substrate.

Figure 1a is a plan view of a conventional example of a vertical MO3 field effect transistor in which a diffusion layer of the opposite conductivity type to the substrate connected to the source electrode is formed under the wire bonding region for the gate electrode. FIG. 2 is a cross-sectional structural diagram taken along line AA' of the conventional example shown in FIG. 1a.

In the conventional example shown in FIG. 1, as a vertical MO8 field effect transistor, an N-type semiconductor substrate 1, which is a drain,
A double diffusion type (so-called DSA type) transistor is shown in which a P type channel 2 and an N type source 3 are formed by diffusion from an end of a gate electrode 4.

In FIG. 1, 1 formed by a method such as selective oxidation
On the thermal oxide film 6 with a thickness of approximately μm, a CV film is provided as an interlayer insulating film.
An oxide film 6 formed by a method such as D is deposited. Source electrode elements are further connected to the oxide film 6 as electrodes for the N-type source 3 and the P-type channel 2 via source contacts 8 . Similarly, a gate electrode wire bonding region 10 is connected to the gate electrode 4 via a gate contact 9. A P-type shield diffusion layer 11 is widely formed in the substrate 1 located under the gate electrode wire bonding region 10 , and is connected to the source electrode 7 via the shield diffusion layer contact 12 . and source electrode 7 are kept at the same potential. S
, G, and D indicate a source terminal, a gate terminal, and a drain terminal, respectively.

The shield diffusion layer 11 is located between the semiconductor substrate 1 which is the drain and the gate electrode wire bonding region 1o, and when the potential thereof is almost the same as that of the source electrode 7, the semiconductor substrate 1 which is the drain The capacitance between the gate electrode wire bonding region 10 and the gate electrode wire bonding region 10 can be reduced. Therefore, the gate-drain capacitance (Cqd), which serves as a feedback capacitance, can be reduced, and the gain is improved.

However, in the conventional example shown in FIG. 1, the resistance of the diffusion layer of the shield diffusion layer 11 is a problem. In other words, if the resistance of the shield diffusion layer 11 is high, the shield diffusion layer 11 located under the gate electrode wire bonding region
The potential of the electrode 6 and the electrode 7 is not completely equal to that of the electrode 7, but rises, and the rate at which the capacitance decreases decreases. Furthermore, the CR time constant increases at high frequencies, and it no longer follows the operating frequency, resulting in a significant reduction in capacitance, and the shield diffusion layer 11 no longer exhibits its original effect.

Furthermore, the bias dependence of the source-drain capacitance (Cds) increases due to the shield diffusion layer 11, resulting in severe input/output impedance changes. 1 size, shield diffusion layer 1
This is because the depletion layer 13 extending from 1 expands and contracts due to the bias voltage between the source and drain, and the depletion layer capacitance changes. When operating a transistor at high frequency and with a large signal, the voltage between the source and drain has a large amplitude, so Cds
Variations in input and output impedance occur due to changes in the input and output impedances, causing problems such as parasitic oscillation and low saturation power, making it extremely difficult to operate the transistor stably.

Furthermore, since the shield diffusion layer 11 requires approximately the same area as the gate electrode wire bonding region 1o, the breakdown voltage of the PN junction with the semiconductor e l:-11' substrate 1, which is the drain, There is a very high possibility that this leakage current will affect the characteristics of the vertical MO8 field effect transistor itself.In addition, the positional relationship between the shield diffusion layer 11 and the transistor should be considered at the design stage in order to ensure voltage resistance, etc. There is also a restriction that we cannot do without it.

Purpose of the Invention The purpose of the present invention is to reduce the capacitance between the gate electrode wire bonding region and the drain up to a high frequency region in a vertical MO3 field effect transistor having a drain on the back surface of a semiconductor substrate, thereby ensuring high gain. . Another object of the present invention is to reduce drain-source capacitance (Cds
) to stabilize the input/output impedance and prevent parasitic oscillation of the transistor.

Structure of the Invention The present invention provides a vertical MO8 with a drain on the back surface of a semiconductor substrate.
In a field effect transistor, a shield electrode made of the same material as the gate and connected to the source electrode is provided on the surface of the semiconductor substrate through an insulating film, and this shield electrode is connected to the gate electrode through the insulating film. It is characterized by forming a wire bonding area and a wiring part for the gate electrode.

DESCRIPTION OF THE EMBODIMENT FIG. 2a is a plan view of an embodiment of the present invention, and FIG.
FIG. 3 is a cross-sectional structural diagram taken along line BB' in FIG.

An explanation will be given by taking a DSA type vertical MO8 field effect transistor as an example of an embodiment of the present invention.

In FIG. 2, components equivalent to those in FIG. 1 are designated with the same reference numbers and symbols.

In the present invention, a shield electrode 14 made of the same material as the gate electrode 4 is formed via an oxide film between the semiconductor substrate 1, which is the drain, and the gate electrode wire bonding region 10. 14 is
It is kept at the same potential as the source electrode by one contact for the shield electrode, reducing Cqd. Shield electrode 14
A thermal oxide film 5'' with a thickness of approximately 1 μm is formed in the same process as the gate electrode 4. The shield electrode 14 is made of the same material as the gate electrode 4, and may be polycrystalline silicon in which impurities are diffused at a high concentration, or high melting point metal silicide such as high melting point metal 2M08i2 such as MO. The resistance of the material of these shield electrodes 14 is more than one order of magnitude lower than the resistance when a diffusion layer is used in the conventional example shown in FIG. Therefore, the potential of the shield electrode 14 can be reliably made equal to the potential of the source electrode, and the potential of the shield electrode 14 located under the gate electrode bonding region 1o hardly floats. Furthermore, since the CR time constant is small, it is possible to track even high frequencies, and the Cqd of the vertical MO3 field effect transistor can be continued to be reduced up to the high frequency region, and the range of operating frequencies can be greatly improved.

Also, according to the present invention, the shield electrode 14 is on the thermal oxide film 5, so the source/drain question and answer -1iiH(Cdg)
The absolute value of and its bias dependence are small. Therefore, the input/output impedance can be improved and stabilized, parasitic oscillation etc. can be prevented, and the saturation power of the transistor can also be improved.

Further, according to the present invention, the shield electrode 14 is expanded 91'--
Since it is an oxide film rather than a diffused layer, problems such as a drop in breakdown voltage with the semiconductor substrate 1, which is the drain, and generation of leakage current are less likely to occur. Therefore, the shield electrode 14 can be formed over the entire area of the gate electrode bonding region 10 and the wiring part to the gate electrode 4 without being influenced by the positional relationship with the transistor or the structure within the substrate, so that the gate-drain capacitance (Cqd ) can be further reduced.

The above description has been given using a DSA type vertical MO8 field effect transistor as an example of the present invention, but if the vertical MO8 field effect transistor has a drain on the back side of the semiconductor substrate and a gate electrode wire bonding region on the front side, It is clear that this method can be applied to all systems and can reduce Cqd and improve high frequency characteristics.

Further, as an embodiment of the present invention, a shield electrode having a smaller area than the gate electrode wire bonding area is shown, but even if the shield electrode is formed wider than the gate electrode wire bonding area, It goes without saying that a similar effect can be obtained in less than 10 microseconds, and that even if it is located under the wiring to the gate electrode, it will have a great effect.

Effect of the invention The present invention brings about the following various effects.

(1) Since the shield electrode is made of the same low resistance material as the gate electrode, the potential of the shield electrode is stable, and Cqd can be reduced even in the high frequency range, resulting in high gain and a wide operating frequency range. A vertical MO3 field effect transistor can be obtained.

(2) )"L' The absolute value of the in-source capacitance (Cds) and its bias dependence are small, the input/output impedance is high, and parasitic oscillation is less likely to occur.

(3) Problems such as breakdown voltage and leakage current between the shield electrode and the semiconductor substrate serving as the drain are less likely to occur.

(4) There is a large degree of freedom in designing the arrangement of the shield electrode.

(6) Realized without changing the manufacturing process 11'
It can be installed without becoming a cost amplifier.

[Brief explanation of the drawing]

FIG. 1(a) is a plan view of a conventional vertical MO3 field effect transistor, FIG. 1(b) is a cross-sectional structural diagram of the same (al) taken along line A-A', and FIG. 2(a) is a plan view of a conventional vertical MO3 field effect transistor. FIG. 2 is a plan view of an embodiment of a vertical MO3 field effect transistor (bl is a cross-sectional structural diagram taken along the line BB' in FIG. ...P type channel node 3...N type source, 4...gate electrode, 6...thermal oxide film, 6...oxide film, 14...
...Shield electrode, 15...Contact for shield electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure (of/2

Claims (1)

[Claims] (1) A shield electrode connected to a source electrode made of the same material as the gate and located on the main surface side of the semiconductor substrate through an insulating film on the main surface of the semiconductor substrate, and an insulating film on the shield electrode. A vertical MO3 field effect transistor characterized in that it has a gate electrode wire bonding region or a part thereof formed through the opposite main surface 75 of the semiconductor substrate, and has a gate electrode wire bonding region or a part thereof formed therein. ? ) Vertical MO3 field effect transistor 0 according to claim 1, characterized in that a gate electrode wiring portion is provided on the shield electrode via an insulating film.