JPS62179760A - Manufacture of photoelectric conversion device - Google Patents

Abstract

PURPOSE:To reduce the size of a sensor cell almost without margin by forming a control electrode region and a main electrode region by self-alignment to enhance the positioning accuracy of the regions. CONSTITUTION:A field oxide film 3 is formed on a silicon substrate 2, with the film as a mask a p-type region to form a base region is formed by self- alignment, an insulation film 7 is further formed, and an electrode 8 of polysilicon is formed thereon. The electrode 8 becomes a gate electrode for the region 4. The electrode 8 is placed partly on the film 3 and has a margin for an alignment margin. Then, with the film 3 and the electrode 8 as masks an n<+> type region 6 which forms an emitter region of impurity density is formed by ion implantation self-alignment. A vertical bipolar transistor is formed of the substrate 2, the regions 4, 6.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a photoelectric conversion device, and particularly to a method for manufacturing a photoelectric conversion device in which an electrode is formed in a control electrode region of a semiconductor transistor with an insulating film interposed therebetween. Regarding the method.

[Prior Art] Conventionally, in semiconductor imaging devices, the cell size of the sensor section, which is a single device, has not been sufficiently small compared to the high integration of the drive circuit section6.
The cell size of a KDRAM is usually about 70 ILm2, whereas in a semiconductor imaging device with a pixel count of 500x500, the cell size is several times larger, 200 to 300p, m2. Increasing the cell size increases the chip area and reduces the number of cracks. Further, since semiconductor imaging devices are generally required to have optical characteristics and analog characteristics compared to digital logic circuit devices, the manufacturing yield is extremely low. For these reasons, the chip unit price of the sensor section is higher than that of DRAM and the like.

There are two main methods for reducing cell size: a scale-down method that proportionally reduces dimensions, and a cell improvement method that reduces cell components. The dimensions of the former method are decreasing with the progress of microfabrication technology, but the rate of decrease is slow at about 0°88 times per year, and rapid reduction cannot be expected. Although the chip area is reduced and the number of defects increases due to
The manufacturing yield decreases due to poor controllability, and as a result, the number of non-defective chips reaches a peak at a certain processing size.

The latter method allows rapid downscaling, for example, RA
In the case of M, what was initially composed of 6 to 8 transistors has now been simplified to 1 transistor and 1 capacitor.

The latter cell improvement method is also effective for semiconductor imaging devices. For example, in a CCD type semiconductor imaging device (hereinafter referred to as CCD type), MOS
It has further improved the simplicity and high integration of the previous model (denoted as "type"), and the isolation of the carrier storage section is performed by an electrically formed potential without relying on a mechanical structure. In addition, in the transfer section, a MOS type source,
A drain region is not required, so higher integration is possible. As described above, although the CCD type allows higher integration than the MOS type, it currently has disadvantages in terms of manufacturing yield. In other words, in the CCD type, if there is a defect in the transfer section, the pixel information of all the corresponding L lines will be affected, and since the inside of the board is used for information transfer instead of the wiring metal, defects in the board will affect the information. However, the current situation is that the CCN type and the MOS type are competing with each other in the field of semiconductor imaging devices. As a semiconductor imaging device that solves these problems and achieves high integration, there is a device using a photoelectric conversion device disclosed in Japanese Patent Application Laid-Open No. 12759/1983.

FIG. 2(a) is a plan view of this photoelectric conversion device.

FIG. 2(b) is a vertical sectional view taken along line A-A'' of the plan view (a).

In FIGS. 2(a) and (b), n+ silicon substrate 1
Photosensor cells are arranged on 2, and each photosensor cell is electrically insulated from adjacent photosensor cells by an element isolation region 13 made of SiO2, 5i3Na, polysilicon, or the like.

Each optical sensor cell has the following configuration.

Low impurity concentration n formed by epitaxial technology etc.
- A p region 15 is formed on the region 14 by doping with a p-type impurity (for example, poron, etc.), and an n0 region 16 is formed in the p region 15 by impurity diffusion technology, ion implantation technology, etc. . P region 15 and n+ region 16 form the base and emitter regions of the bipolar transistor, respectively.

An oxide film 17 is formed on the p region 15 and the element isolation region 13 in which each region is formed in this way.
An electrode 18 having a predetermined area is formed thereon. This electrode 18 faces p-region 15 with oxide film 17 in between, and applies a pulse voltage to electrode 18 to control the potential of p-region 15 in a floating state.

In addition, an emitter electrode 19 connected to the n+ region 16
．． Wiring 20 for reading signals from the emitter electrode 19 to the outside
, wiring 21 connected to electrode 18, n+ silicon substrate 1
On the back surface of 22.2, there is an n medium region 22.2 with high impurity concentration. and an electrode 23 for applying a potential to the collector of the bipolar transistor.

The operation of the photoelectric conversion device will be described below.

When the light 24 is incident, electron-hole pairs corresponding to the amount of light are generated in the semiconductor, and the electrons are biased to a positive potential.
The holes flow out from the silicon substrate 12 side, but the holes are p
The base potential increases due to the accumulated holes that are accumulated in the region 15 (accumulation operation). The base potential is further increased by applying a voltage between the n+ region 16, which is the emitter region, and the n+ silicon substrate 12, which is the collector, and by applying a positive voltage to the electrode 18. By reading this potential change as a collector current, it is possible to obtain an electrical signal corresponding to the amount of incident light (readout operation)
, and to remove the charges accumulated in the p region 15,
It is sufficient to ground the emitter electrode 19 and apply a positive voltage pulse to the electrode 18. By applying this positive voltage, the p region 15 is forward biased with respect to the n middle region 16, and the accumulated charge is is removed (refresh operation). Thereafter, the above-described storage, readout, and refresh operations are repeated.

[Problems to be solved by the invention] However, the number of pixels using the above photoelectric conversion device is 500.
Even in the X500 semiconductor imaging device, the cell size was as large as approximately 200 JLm2, which was insufficient for high integration.

[Means for solving the problem] The above problem is solved by forming a field insulating film on a semiconductor substrate in a method for manufacturing a photoelectric conversion device in which an electrode is formed in a control electrode region of a semiconductor transistor via an insulating film. a step of forming a control electrode region by a self-line method using the field insulating film as a mask; a step of forming an insulating film on the control electrode region and forming an electrode thereon;
The problem is solved by the method for manufacturing a photoelectric conversion device of the present invention, which includes a step of forming a main electrode region by a self-line method using the field insulating film and the electrode as a mask.

[Function] The method for manufacturing a photoelectric conversion device of the present invention uses the self-line method to form the control electrode region and the main electrode region, thereby increasing the positional accuracy of the control electrode region and the main electrode region, and almost reducing the margin. Since you can create each area without taking
The cell size of the sensor cell can be reduced.

[Example] Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is an explanatory diagram of a sensor cell of a semiconductor imaging device according to the method of manufacturing a photoelectric conversion device of the present invention, in which (a) is a plan view, and (b) is a cross-sectional view taken along line A-A' in the plan view (a). . In this embodiment, the semiconductor transistor is a bipolar transistor, the control electrode region is the base region, and the main electrode region is the emitter region.

In FIG. 1, 1 is a sensor cell, and CZN (1
00) A field oxide film 3 having a thickness of lILm is formed on a 10 Ω-cm silicon substrate 2 by the LOCO3 method. If necessary, an n+ channel stopper 5 is formed under this field oxide film 3. The n+ channel stopper 5 serves to prevent the inflow of holes from adjacent sensor cells. ! 3 as a mask, impurity concentration IQ + 67 cm by self-line method.
3. Form a p region 4 forming a base region with a diffusion depth of 0.81 Lm. Here, the basic dimension (minimum processing dimension) is the length of one side of contact hole 11, which will be described later, and the size of p region 4, which is the active area, is 3×2 times the basic dimension. Furthermore, an insulating film 7 such as an oxide film with a thickness of 500 ml is formed, and an electrode 8 of polysilicon with a thickness of 4000 ml is formed thereon. This electrode 8 becomes a gate electrode for p region 4. The electrode 8 partially rests on the field oxide film 3 and has a margin for misalignment. Next, using the field oxide film 3 and the electrode 8 as a mask, the ion implantation self-line method is used to form an impurity with an impurity concentration of 1019/cm3 and a diffusion depth of 0.
An n medium region 6 forming a 3 pm emitter region is formed.

Silicon substrate 2 + P region 4 and n medium region 6,
A vertical bipolar transistor is formed. hrc is t
It's about ooo. Next, a PSG interlayer insulating film 9 with a thickness of 7,000 thick is formed, a contact hole 11 is opened, and a wiring metal 10 with a thickness of 8,000 thick is electrically connected to the n medium region 6.

According to this embodiment, the cell area has a basic dimension of 2ILm.
1010×8=801 L, which is comparable to the cell area of 70 m2 of 256K DRAM whose basic dimensions are 2 gm. Also, compared to the cell area of 200 to 300 ILm2 of a conventional semiconductor imaging device, the size is approximately 1/3. Further, the aperture ratio excluding the electrode 8 and the wiring metal 10 is 51%, which is a value that is sufficient for use.

In this example, since the LOCO3 method is used to form the field oxide H3, the surface is flat and microfabrication in the post-process is easy. Also, p region 4. Since the self-line of the field oxide 11j3 is used to form the blue region of the n+ region 6, alignment errors do not occur, and therefore the characteristics of the bipolar transistor do not vary and are stable. Furthermore, since the n+ region 6 is formed by the self-alignment of the electrode 8, the P region 4 forming the active area can be formed with the minimum necessary area, and no extra gate emitter parasitic capacitance is generated. Since the electrode 8 and the transistor active region of the p region 4 forming the base region can be formed very close to each other, various parasitic effects caused by excessive base resistance can be suppressed. Also.

Since the active area, that is, the p-region 4 can be formed with a minimum amount, the base and collector capacitances can be reduced, and the device characteristics are improved.

As another embodiment of the present invention, a conventional photoetching method may be used instead of the LOCO3 method to form the field insulating film 3, and although it is disadvantageous for planarization, there is no bird's beak etc. in the LOCO3 method. Highly accurate base area and emitter area can be obtained. If this embodiment is used, the transistor characteristics will be more stable without variations.

In addition, as another embodiment, another substrate may be added to the silicon substrate 2,
For example, by using an epitaxial substrate or the like, it is also possible to simultaneously form NMOS and the like.

Also, if you want to further improve the aperture ratio.

In the above embodiment, the sensor cell may be made larger than 5×4 times the basic size. In this case, it is advantageous for the aperture ratio to arrange the p region 4 as close to the corner of the sensor cell as possible.

Further, the material of the electrode 8 and the wiring metal IO may be any material such as polysilicon At, A1 alloy, high melting point metal, silicide, etc. Regarding the insulating film 7, oxide film, nitride film, etc.
It's optional.

[Advantageous Effects of the Invention 1] As explained in detail above, according to the method for manufacturing a photoelectric conversion device of the present invention, the control electrode region and the main electrode region are formed by using the self-line method. To provide an inexpensive photoelectric conversion device which can reduce the cell size of a sensor cell, has a high yield, and can improve the positional accuracy of main electrode regions and create each region with almost no margin. INDUSTRIAL APPLICABILITY The present invention is suitably used in semiconductor imaging devices and the like that require high integration.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of a sensor cell of a semiconductor imaging device according to the method of manufacturing a photoelectric conversion device of the present invention, (&) is a plan view, and (b) is a cross-sectional view taken along line A-A' of the plan view (&). . FIG. 2(a) is a plan view of the photoelectric conversion device, and FIG. 2(b) is a vertical sectional view taken along the line AA' of the plan view (a). 1...Fist/Sensor cell 2...Fist...Silicon substrate 3...Field oxide film 4/Fist...P region 5...N+ channel stopper 6... Dispute...N10 area 7...Insulating film 8, II+1...-Electrode agent Patent attorney Seki Yamashita Figure 1 Figure 2

Claims (1)

[Claims] A method for manufacturing a photoelectric conversion device in which an electrode is formed in a control electrode region of a semiconductor transistor via an insulating film, comprising: forming a field insulating film on a semiconductor substrate; and masking the field insulating film. a step of forming a control electrode region by a self-alignment method; a step of forming an insulating film on the control electrode region and forming an electrode thereon;
A method for manufacturing a photoelectric conversion device, comprising the step of forming a main electrode region by a self-alignment method using the field insulating film and the electrode as a mask.