JPH02137235A - Charge transfer element and manufacture thereof - Google Patents

Abstract

PURPOSE:To avoid any positional slip between shielding regions and a high concentration region by a method wherein, after forming the shielding regions, the high concentration semiconductor region is formed by ion implanting a semiconductor substrate using the shielding regions as masks. CONSTITUTION:N-Well regions 21 are formed simultaneously with the transfer channel 22 of a charge transfer part 4 by implanting ion into a P-type semiconductor substrate 20. Shielding regions 50 as well as an output control electrode 24 and a reset electrode 31 are simultaneously formed of poly-Si respectively during the formation process of the first and the second layer transfer electrode 25. Next, a floating diffused layer 10' and a diffused layer 28 are formed by impurity P<+> ion into the N-Well region 21 using the shielding regions 50, the output control electrode 21 and the reset electrode 31 and a resist as masks, and then an insulating film 25 is formed while contact holes 26', 29 are made in the diffused layer 10' and 28. Then, an Al wiring is formed to connect a resist drain RD to output circuit. Through these procedures, the space of the floating diffused layer 10' can be minimized to reduce the capacity in this region so that the output sensitivity of a charge transfer element may be augmented.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a charge transfer device such as a COD shift register and a method for manufacturing the same.

2. Description of the Related Art A schematic diagram of a conventional frame transfer type CCD solid-state imaging device is shown in FIG. The CCD solid-state image sensor (1) is equipped with an imaging section (2) and a storage section (3), and a horizontal register (4) is connected to the storage section (3). The obtained image charge is transferred and accumulated in the storage section 3) and sequentially sent out via the horizontal register (4).The image charge sent out from the horizontal register (<4) is transferred to the output section (5). It is converted into a voltage value and output as an image signal Y (t).

The output section (5) is composed of a reset transistor (6) and a source follower type output circuit (7) (8) connected in two stages, and the image charge from the horizontal register <4) is transferred to the floating reset transistor <6). It is received by the diffusion layer (10). The floating diffusion layer (10) is set to a predetermined reference potential at regular intervals according to the reset pulse φ applied to the gate of the reset transistor (6), and is also set to a predetermined reference potential at a constant cycle according to the reset pulse φ applied to the gate of the reset transistor (6). A pair of MOS connected in series between the input, i.e. power supply and ground
It is connected to the power supply side gates of FET (7a) (7b). And a pair of MO8F ET (7a) (
The connection point 7b) is connected to the power supply side gates of a pair of MOSFETs (8a) (8b) connected in series between the power supply and ground. This pair of MOSFETs (8a)
(sb) constitutes a second stage source follower type output circuit. Therefore, the image signal Y (t) synchronized with the reset pulse φ1 is transmitted to the second stage MOSFETs (8a) (8b).
output from the connection point.

FIG. 4 is a plan view showing the structure of the reset transistor (6) from the output end of the horizontal register (4), and FIG. A cross section taken along the Y' line is shown in FIG. 5(b).

The N-well region (21) provided in the P-type semiconductor substrate (20) is connected to the transfer channel (2) of the horizontal register (4).
2), and is formed at the same time as the transfer channel (22). On the transfer channel (22), there is a transfer electrode (22) having a two-layer structure in a direction perpendicular to the image charge transfer direction.
3) has been completely formed, and this transfer electrode (23) is pulse-driven by the horizontal transfer pulse x d )I. An output control electrode (24) is provided at the final stage of the horizontal register (4), and a constant control voltage V is applied to this output control electrode (24).
. By applying 0, a predetermined potential barrier is formed at the output end of the horizontal register (4). On the opposite side of the output control electrode (24) from the transfer electrode (23),
An N+ floating diffusion layer (10) is provided, and a horizontal resistor (10) is provided in this floating diffusion layer (10).
The image charge from 4) is temporarily held. Further, since the floating diffusion layer (10) is connected to the above-mentioned output circuit (7), a contact hole (26) is provided in the insulating layer (25) on the floating diffusion layer (10) as shown in FIG. ) AP wiring (27) is formed. moreover,
A second N+ type scattering layer 28) is formed in the N-Well region (21) at a predetermined distance from the floating diffusion layer (10), and this second diffusion layer (28) is reset. Connected to drain RD. In addition, the second diffusion layer (
28) The upper insulating layer (25) also has a hole hole 26
) are provided, and 12 wirings (3o) are formed. Then, a floating diffusion layer (10) and a second diffusion layer (28) are formed.
) A reset electrode (31) is provided between the re-diffusion layers (10) and (28) to control conduction between the re-diffusion layers (10) and (28). The reset electrode (31) and the rediffusion layers (10) and (28) constitute a reset transistor (6), and the reset electrode (31)
) is applied to the reset pulse ≠.

Accordingly, the image charges held in the floating diffusion layer (10) are discharged to the reset drain RD.

In addition, in FIG. 4, the Aj2 wiring (27) (30) is omitted.

(c) Problems to be Solved by the Invention In an element equipped with the output section (5) as described above, in order to improve the output sensitivity, a blotting diffusion layer (10) is used.
capacity, floating diffusion layer 10〉 and output circuit (7
) and the capacitance of A1 wiring (27〉) and the output circuit (
7) It is desired to reduce the gate capacitance of the MOSFET (7a) in the device. Among these, reducing the capacitance of the floating diffusion layer (10) reduces the capacitance of the AP wiring (27) and MO
This method has a greater effect of improving sensitivity than reducing the gate capacitance of the SFET (7a), and is commonly used.

The most effective way to reduce the capacitance of the floating diffusion layer (10) is to reduce the area of the floating diffusion layer (10), and for this reason, the floating diffusion layer (10) is formed to be as narrow as possible. Ru. However, the floating diffusion layer (10) has an output circuit (7).
It is necessary to connect the Afl wiring (27) for connection to the floating diffusion layer (10), and it is necessary to form a contact hole (26) on this floating diffusion layer (10). For example, the design rule is 1, which requires at least 3 times the width.
．． In the case of 5 μm, the width of the contact hole (26) is at least 1.5 μm, and the width of the bloating diffusion layer (
The width of 10) can only be narrowed to about 3.0 to 4.5 μm. Therefore, in the conventional structure shown in FIGS. 4 and 5, the area of the bloating diffusion layer (10) cannot be reduced below a certain level, and if the area of the bloating diffusion layer (10) is Even if the size is sufficiently reduced, extremely precise mask alignment is required, and no improvement in manufacturing yield can be expected.

Therefore, an object of the present invention is to sufficiently reduce the area of the floating diffusion layer (10) to reduce the capacitance, and to enable manufacturing in a normal process that does not require extremely precise mask alignment. .

(d) Means for solving the problems The present invention has been made to solve the above problems,
a charge transfer section provided on one main surface of a semiconductor substrate of one conductivity type to transfer information charges; an output control electrode provided at an output end of the charge transfer section to control output of information charges from the charge transfer section; a highly concentrated semiconductor region of a reverse conductivity type that is provided adjacent to the output control electrode and holds information charges output from the charge transfer section for a certain period of time; A reset electrode is provided for discharging information charges in the semiconductor region at regular intervals, and is provided in an island shape between the output control electrode and the reset electrode on both ends of the semiconductor region in the width direction with an insulating film interposed therebetween. a shielding region that can serve as a mask for ion implantation, and a detection means electrically connected to the semiconductor region to detect the potential of the semiconductor region as a voltage value. A contact hole is provided in a region limited by the electrode and the shielding region, and connects the detection means, and is provided from the semiconductor region to the shielding region.

The method for manufacturing the charge transfer device includes a step of forming the charge transfer portion on a semiconductor substrate, a step of forming the shield region in an island shape in parallel with the charge transfer portion, and a step of forming the shield region in an island shape in parallel with the charge transfer portion. forming the output control electrode and the reset electrode insulated from the transfer electrode and the shielding region;
implanting ions into the semiconductor substrate using the shielding region, the output control electrode, and the reset electrode as a mask to form the high concentration semiconductor region of a conductivity type opposite to that of the semiconductor substrate; The method is characterized by comprising the step of providing a hole in the insulating film from the semiconductor region to the shielding region.

(E) Effect According to the present invention, the area of the high concentration semiconductor region is reduced by the area limited by the shielding region formed in an island shape on this region, and the capacitance of the high concentration diffusion region is reduced by that amount. Since this decreases, the output sensitivity of the charge transfer device improves.

Further, according to the manufacturing method of the present invention, since the high-concentration semiconductor region is formed by forming the shielding region and then implanting ions using the shielding region as a mask, there is no misalignment between the shielding region and the high-concentration region. By providing a contact hole from the heavily doped semiconductor region to the shielding region, a connection to the heavily doped region can be reliably obtained regardless of the width of the heavily doped diffusion region.

(f) Example An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of the charge transfer device of the present invention, and FIG. 2 is a cross section taken along the line xx' of this figure. In this figure, the charge transfer section (4') is the horizontal register (4') in Figures 4 and 5.
4), and the same parts are given the same reference numerals.

On the N-well region (21) on the opposite side of the output control electrode (24) from the transfer electrode (23), island-shaped shielding regions (50) (50) are formed at both ends in the width direction. A reset electrode (31) is formed across the N-well region on the side of the shielding region (50) opposite to the output control electrode (24). Then, the output control electrode (24
) and the reset electrode (31), a shielding region (
50) An N" type floating diffusion layer (10°) is formed in the region excluding (50). The floating diffusion layer (10') is formed in the insulating layer (25) on this floating diffusion layer (10'). ) is provided with a contact hole (26') for connecting the wiring.This contact hole (26') is formed from the floating diffusion layer (10') to the shielding region (50) (50). On the shielding area (50) (50), the shielding area (50) (50)
The contact hole (26')
reaches the floating diffusion layer <io'> only in the portion between the two shielding regions (50) (50). Therefore, this contact hole (26') is
By forming the J2 wiring (27'), a connection between the floating diffusion layer (10') and the output circuit (7) is obtained. Furthermore, a second diffusion layer (28) similar to that shown in FIG. A contact hole is formed in the insulating layer (25) on the diffusion layer (28).

According to the above configuration, the floating diffusion layer is 10°)
Compared to the conventional floating diffusion layer (10), the area limited by the shielding regions (50) (50) is reduced (/J) and the capacitance is reduced, so the output sensitivity is improved.

Next, the manufacturing method will be explained.

The N-Well region (21) is a P-type semiconductor substrate (20
) By implanting P'' ions into the charge transfer section (4゛)
is formed at the same time as the transfer channel (22). and,
When forming the first layer transfer electrode (23), the shielding region (50
>(50) is formed using Poly-5i, and when the second layer transfer electrode (23) is formed, the output control electrode (24) and the reset electrode (31) are simultaneously formed using Poly-5i. Between these first and second layers, there is a
Since an insulating film such as
) and the output control electrode (24) or the shielding area (50
)(so> and the reset electrode (31) will not be short-circuited, and the distance between them can be made extremely short.

After the shielding regions (50), output control electrodes (24), and reset electrodes 31) are formed as described above, N
- A floating diffusion layer (10') and a second diffusion layer <28) are formed by implanting P'' ions into the well region (21). After this, an insulating film (2
5), and contact holes (26') (29) are provided on the bloating diffusion layer (10') and the second diffusion layer (28) by etching. The contact hole (26') on the floating diffusion layer (10') is
Bloating diffusion layer (10') to shielding region (50)
(50) is etched and provided. At this time, only the insulating film (25) is etched, and the shielding area (
50) If an etching method is used in which Po1y-5i of (50) is not etched, two shielded regions (5
0) (50) floating diffusion layer (10'
) A contact hole (26') is obtained.

Then, AP wiring is formed in the contact hole (26'>(29)) to connect the reset drain RD and output circuit (7).
A connection is established.

In the above manufacturing method, the shielding regions (50) (50)
Since no misalignment occurs between the contact hole (26') and the floating diffusion layer (10'), the contact hole (26') is formed in the shielding region (5').
0) (50).

Therefore, the width of the floating diffusion layer (10') does not need to take into account misalignment, and can be formed sufficiently thin. For example, if the design rule is 1.5 μm, a floating diffusion layer (10′) with a width of 1.5 μm can be formed. This width is less than half that of the conventional one shown in FIG.

In this example, the shielding regions (50) and (50) are made of Poly-5i, but it can be used as a mask for ion implantation, and any material other than the insulating film may be used. < , it is not limited to Po1y-5i. However, the transfer electrode (23) of the charge transfer section (4゛)
If a different material is used, the transfer electrode (23) and the shielding regions (50) (50) cannot be formed at the same time, resulting in an increase in the number of steps.

Effects of the Invention According to the present invention, it is possible to reduce the area of the highly doped semiconductor region (floating diffusion layer) to a minimum, and the capacitance of this region can be significantly reduced. ,
The output sensitivity of the charge transfer element can be improved, and if this charge transfer element is employed in the horizontal register section of a CCD solid-state image sensor, a highly sensitive image sensor can be obtained.

Further, according to the manufacturing method of the present invention, there is no need for extremely precise mask alignment, and the manufacturing yield does not decrease even though the width of the high concentration semiconductor region is narrowed to the minimum.

[Brief explanation of the drawing]

Fig. 1 is a plan view showing one embodiment of the present invention, and Fig. 2 is a plan view showing an embodiment of the present invention.
3 is a schematic plan view of a conventional CCD solid-state image sensor, FIG. 4 is a plan view of a horizontal register section, and FIG. 5 is a sectional view of FIG. 4. (1)...COD, (4)...Horizontal register,
(5)...Output section, (6)...Reset transistor, (7)(8)...Output circuit, (10)(
10')...Floating diffusion layer, (26)(2
6°)...Contact hole, (31)...Reset electrode, (50)...Shielding region.

Claims (3)

[Claims] (1) A charge transfer section provided on one main surface of a semiconductor substrate of one conductivity type to transfer information charges; and an output control provided at the output end of this charge transfer section to control the output of information charges from the charge transfer section. an electrode, a high concentration semiconductor region of opposite conductivity type provided adjacent to the output control electrode and holding the information charge output from the charge transfer section for a certain period of time, and a side of the semiconductor region opposite to the output control electrode side; a reset electrode that is provided adjacently and discharges information charges in the semiconductor region at regular intervals; a shielding region provided in a shape that can serve as a mask for ion implantation; a detection means electrically connected to the semiconductor region to detect the potential of the semiconductor region as a voltage value; A charge transfer element, wherein the charge transfer element is provided in a region limited by an electrode, the reset electrode, and the shielding region, and a contact hole for connecting the detection means is provided from the semiconductor region to the shielding region. (2) The method for manufacturing a charge transfer device according to claim 1, including the step of forming the charge transfer section on a semiconductor substrate, and forming the shielding region in an island shape in parallel with the charge transfer section. forming the output control electrode and the reset electrode insulated from the transfer electrode and the shielding region of the charge transfer section; and using the shielding region, the output control electrode, and the reset electrode as a mask to form the semiconductor implanting ions into the substrate to form the high concentration semiconductor region having a conductivity type opposite to that of the semiconductor substrate; and providing a contact hole from the semiconductor region to the shielding region in an insulating film provided on the shielding region. A method for manufacturing a charge transfer device, comprising the steps of: (3) The method of manufacturing a charge transfer element according to claim 2, wherein the transfer electrode of the charge transfer section and the shielding region are formed in the same step.