JPS62577B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit, and particularly to the structure of a semiconductor device having an epitaxial layer on the same substrate having an epitaxial layer having a uniform overall thickness but varying in thickness depending on withstand voltage. .

Furthermore, the technology related to the present invention is disclosed in Japanese Unexamined Patent Publication No. 52-
It is disclosed in Publication No. 69587.

However, the technique described in Japanese Patent Application Laid-Open No. 52-69587 does not take into account the structure of the buried layer.

Hereinafter, the present invention will be explained in detail with reference to Examples. As an example, a high voltage transistor with collector-emitter breakdown voltage (BV _CEO ) of 150V and BV _CEO =
We will explain the case of integrating 15V low voltage transistors (small signal) on the same substrate.

First, the required specific resistance ρ _EP and thickness t _EP of the epitaxial layer will be described. In order to form a high voltage transistor with the above specifications, if the maximum value of the transistor's DC current amplification factor h _FE is 200, then ρ _E
P must be 12 Ωcm or more, and it is set to 15 Ωcm to allow for margin in the manufacturing process. The thickness of the epitaxial layer at this time is based on the base-collector reverse bias of 150V.
Taking into consideration the thickness of the depletion layer extending in , it is 30 μm. Also, if the thickness of the epitaxial layer forming the low voltage transistor is found in the same way, it is 10 μm.
It is enough.

Referring to FIG. 1, a case will be described in which a structure with the above specifications is formed using the manufacturing process of the present invention. Figure 1 shows that after an oxide film 2 is formed on a silicon substrate 1 having a surface with a crystal orientation of (100), a rectangular window consisting of only sides parallel to the <100> crystal axis direction is formed in this oxide film 2 using photo-etching technology. FIG. The same numbers below refer to the same item.

In the same figure, approximately 20 μm was etched using an anisotropic etching solution.
A recess 21 with a depth of m is formed in the substrate. The etching solution is a mixture of a 20wt% KOH aqueous solution, isopropyl alcohol, and a surfactant such as FC-95 to prevent pyramid-shaped protrusions from appearing on the etched surface. 300g of KOH, 1200c.c. of pure water, and 300c of isopropyl alcohol. .c., prepared with 25 c.c. of 0.1% aqueous solution of FC-95. To etch 20μm,
Using this mixed etching solution, it takes about 50 minutes at a solution temperature of 70°C.

Next, in the same figure, after forming the recessed portion as described above, the buried n ⁺ diffusion layer 3 is formed.

Note that the buried diffusion layer 3 has a portion 31 extending to the substrate surface around the recess. Next, an n-type epitaxial layer 4 is grown to a thickness of 30 μm, and an oxide film 42 of an etching masking material is formed only on the concave portions 41 of the epitaxial layer where the concave portions of the substrate have been transferred.
is formed by normal photoetching. At this time, the oxide film 42 may have a portion covering the upper part of the recess by about 5 to 10 μm, as indicated by the broken line in the figure.

In FIG. 1, the epitaxial layer on the lower voltage side is etched using an anisotropic etching solution to flatten the surface. The epitaxial layer is now a high voltage part.
The thickness is 30μm, and the low voltage part is 10μm thick. The etching solution used was a 40wt% KOH aqueous solution, and the etching was carried out at a temperature of 70°C for about 30 minutes.

After planarization, the oxide film 42 remaining in the etching process is removed. Surface oxidation is performed to form a SiO ₂ film (not shown) on the surface of the epitaxial layer, and windows for isolation diffusion are opened in the SiO ₂ film by photoetching. P for isolation
The high breakdown voltage section 101 and the low breakdown voltage section 102 are separated by the type diffusion layer 5 as shown in FIG. 1, and the subsequent steps are carried out in a normal linear integrated circuit manufacturing process to form an integrated circuit having the structure shown in the same figure. 6 is a collector punched n ⁺ diffusion layer connected to the buried layer 3 at a portion 31; 7
8 is a P-type base diffusion layer, and 8 is an n-type emitter diffusion layer.

In the semiconductor device of the present invention, the island region 4 of the high breakdown voltage section
Since the collector buried diffusion layer 3 of No. 01 extends on the substrate surface around the recess, the collector is not punched out.
The n ⁺ diffusion layer 6 can be easily formed in the same process as that of the island region 402 of the low breakdown voltage section. Furthermore, since the collector punched n ⁺ diffusion layer can be formed in a thin epitaxial layer, there is no need to increase the occupied area unnecessarily, and the integration density of the integrated circuit is not adversely affected.

As described above, in the semiconductor device of the present invention,
The device is characterized in that a collector buried layer for reducing collector resistance is provided in the surface area around the concave portion of the substrate.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the manufacturing process of an embodiment of the semiconductor device of the present invention. 1: P type Si substrate 2: SiO ₂ film 3: n ⁺ type collector buried layer 4: n type Si epitaxial layer, 6: n ⁺ collector punching layer.

Claims (1)

[Scope of Claims] 1. A semiconductor substrate of a first conductivity type, a recess provided in the substrate, a first impurity region of a conductivity type opposite to that of the substrate provided in a surface region of the recess, and a recess provided in the recess. In a semiconductor device having a semiconductor layer filled in the substrate and a semiconductor layer provided on the surface of the substrate and having a substantially flat surface, at least one high-voltage element is provided at a position corresponding to the recessed portion, and corresponds to a portion other than the recessed portion. At least one low breakdown voltage element is provided at a position where the first impurity region is provided, and the first impurity region is provided so as to extend into the substrate surface region around the recess before the semiconductor layer is provided. , and a second conductivity type opposite to that of the semiconductor substrate, which is provided from the surface of the semiconductor layer toward the semiconductor substrate.
A semiconductor device, wherein the impurity region and the first impurity region are in contact with each other.