JP2654383B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of manufacturing a high-withstand-voltage power IC coexisting with a logic circuit and a small signal circuit. The present invention relates to a method for manufacturing a semiconductor device suitable for being integrated on a chip.

[Conventional technology]

Conventionally, a semiconductor device in which a high voltage power MOSFET and a logic circuit or a small signal control circuit coexist is described in Electronic Design February 21, 1985, pp. 191 to 198 (Electronic Design February 21, 1985 pp. 191-198). It has been reported.

[Problems to be solved by the invention]

In the above prior art, as shown in FIG. 2, a drain terminal D of a power MOSFET is connected to an n ⁺ substrate 21 by a deep high impurity concentration n ^{+ type} buried diffusion layer 26 penetrating through a p-type epitaxial layer 22.
Is taken from. In this structure, the power MOSFET
P-type epitaxial layer separating the 24 from the Bi-CMOS circuit 25
The withstand voltage of the island surrounded by 22 and the p ^{+ type} element isolation diffusion 27 is
It was mainly limited by the thickness of the p-type epitaxial layer 22.
This is because it cannot be made thicker than the depth of the n ^{+ type} buried diffusion layer 26. Therefore, so as not to reduce the effective thickness of the p-type epitaxial layer 22, the Bi-CMOS circuit portion 25, has failed has established a conventional thin n ⁺ buried layer. Therefore, the series resistance of the npn transistor increases, and the frequency characteristics decrease accordingly.
Furthermore, reduction in growth and CMOS portion Ratsuchiatsupu immunity of the parasitic pnp of h _FE, there is a problem and the like.

An object of the present invention is to provide a method of manufacturing a semiconductor device in which a high breakdown voltage low on-resistance power MOSFET and a control circuit section including a logic circuit and a small signal section can coexist on the same chip under optimum structural conditions. To provide.

[Means for solving the problem]

The object is to form a concave portion by etching an antimony-doped n ⁺ substrate on which a phosphorus buried layer has been formed in advance, and form a p-type epitaxial layer on this n ⁺ substrate so as to be substantially flat, The p-type epitaxial layer other than the concave portion is formed by the rise of the phosphorus buried layer diffused into the n ⁺ substrate,
This is achieved by connecting to the antimony-doped n ⁺ diffusion layer formed on the surface of the p-type epitaxial layer to make it n-type.

[Action]

By etching the n ⁺ substrate of the Bi-CMOS circuit forming portion to provide a concave portion, the thick p-type epitaxial layer can be formed without increasing the diffusion time of high-temperature long-time diffusion for forming a deep n ^{+ -type} through diffusion layer. The layer and the n ⁺ penetrating layer can coexist.

Since a thick p-type epitaxial layer can be used, a conventional antimony-doped n ⁺ buried layer can be formed in the Bi-CMOS circuit, reducing the collector series resistance of npn and reducing parasitic p.
reduction of np of h _FE, can improve element characteristics.

Moreover, a high isolation breakdown voltage can be ensured by the thick p-type epitaxial layer.

Furthermore, since the n-type epitaxial layer may be grown on the flat p-type epitaxial layer and on the antimony-doped n ⁺ buried layer, the thickness variation due to the buried phosphorus and the resistivity due to the auto-doping. It can be formed with high accuracy with little influence of variation.

Since the phosphorus buried layer may be formed on the entire surface of the n ⁺ substrate,
A photomask for forming the phosphorus buried layer can be omitted, and the cost can be reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS.

Here, 60V class n-channel vertical power MOSFET
An example is an IC structure in which a circuit and a Bi-CMOS circuit coexist.

In order to use a 60V class n-channel vertical power MOSFET with low on-resistance, the gate voltage must be applied sufficiently high, and the gate and drive circuits must be 10V higher than the drain voltage
Handle moderately high voltages. Therefore, a high withstand voltage element of 70 V must also be formed in the circuit section. In the end, the circuit section coexisting with the n-channel vertical power MOSFET of the 60 V class needs to have a separation withstand voltage of at least 70 V or more. With a design margin of about 15%, we aim for a breakdown voltage of 80V.

When a high voltage is applied to the drain of the power MOSFET of FIG. 1, that is, the substrate 1, the depletion layer spreads into the n-type epitaxial layer 4 and the p-type epitaxial layer 3 of the power MOSFET portion. Similarly, a high withstand voltage element (not shown, for example, a p-channel lateral high withstand voltage MOS having an offset structure)
Or n-channel vertical high voltage DMOS or high voltage lateral pn
Even when a high voltage is applied to the p-type transistor, the depletion layer spreads in the n-type epitaxial layer 4 and the p-type epitaxial layer 3. Therefore, in order to ensure the isolation breakdown voltage, a depletion layer extending from n ⁺ substrate 1 and a thick p-type epitaxial layer 3 that does not punch through the depletion layer extending from n ⁺ buried layer 5 are required.

Considering a separation withstand voltage of 80 V, the p-type epitaxial layer 3 has a high resistivity of at least 2.5 Ωcm. 8
The depletion layer extending into the p-type epitaxial layer 3 when 0 V is applied is about 5 μm in a step junction approximation. Assuming that the diffusion depth of n ⁺ buried layer 5 is 7 μm, the rise from n ⁺ substrate 1 is also 7 μm, so that the minimum required p-type epitaxial layer 3 is formed.
Is 24 μm or more. However, at this thickness, the p-type epitaxial layer 3 is almost in a pinch-off state. Therefore, when a substrate current flows through the p-type epitaxial layer 3 due to the operation of the parasitic sub-pnp or the like, a potential drop occurs, and the parasitic npn And the thyristor may operate, possibly leading to destruction. Therefore,
The thickness of the p-type epitaxial layer 3 has a sufficient margin,
40 μm or more.

With reference to FIG. 3, an example of a manufacturing method for realizing the structure of FIG. 1 having the above specifications will be described.

In FIG. 3 (A), an n-type layer 51 is formed on the entire surface of the antimony-doped n-type (100) silicon substrate 1 having a resistivity of 0.02 Ω · cm or less by performing high concentration phosphorus deposition or phosphorus ion implantation without using a mask.

After the surface is oxidized as shown in FIG. 3B, a window is opened by removing the oxide film 2 in a portion to be a circuit portion by ordinary photolithography technology. At this time, the pattern of the photomask is a rectangular pattern parallel to the <100> direction.

In FIG. 2C, a recess having a depth of about 20 μm is formed by performing anisotropic etching for about 30 minutes using, for example, an aqueous solution of KOH of 40 wt% at 70 ° C. using the oxide film 2 as an etching mask.

FIG. 3D shows a state in which the p-type epitaxial layer 3 is grown to a thickness of about 45 μm thicker than the depth of the concave portion after removing the oxide film. In order to obtain a structure having a flat surface in FIG. 3 (E) from this state, for example, a “method of manufacturing a semiconductor device” previously proposed by the present applicant (Japanese Patent Publication No.
-43903). Alternatively, planarization may be performed using a polishing technique. In this case, it is not necessary to form a rectangular pattern parallel to the <100> direction described with reference to FIG.

In FIG. 3 (E), the thickness of the p-type epitaxial layer 3 is about 20 μm in a thin part and about 40 μm in a thick part.

In FIG. 1F, antimony is deposited on the power MOS portion and the circuit portion using the oxide film 2 as a mask.

In FIG. 3G, the n ⁺ buried layer 5 is extended and diffused. When performed at 1200 ° C for about 15 hours, antimony-doped n ⁺
The diffusion depth of the buried layer 5 is about 7 μm, and the rise of the phosphorus buried layer 51 is about 15 μm. Therefore, the power MOS section is n
⁺ Buried layer 5 and phosphorus buried layer 51 are connected to n ⁺ substrate 1.

In FIG. 3H, an n-type epitaxial layer 4 required for a 60 V power MOS is grown under the conditions of 0.9 Ωcm and 12 μm.

In FIG. 1I, after the surface is oxidized, a window is opened in the oxide film 2 by photoetching, and boron is deposited for p-type separation and diffusion.

In FIG. 10 (J), a channel stopper or a deep n-type diffusion layer 53 for reducing the collector series resistance of npn is formed. At this time, the p-type separation / diffusion layer 6 reaches the p-type epitaxial layer 3, and the island separation by the pn junction is completed.

From the same figure (J) and thereafter, as shown in the same figure (K), the same n-channel vertical as that of the simple substance is provided in the n-type epitaxial layer 4 connected to the n ⁺ substrate 1 by the n ⁺ buried layer 5 and the phosphorus buried layer 51. Type power MOSF
An ET is formed, and a Bi-CMOS or the like is formed in the n-type epitaxial layer 4 separated from the island on the p-type epitaxial layer 3,
Constructs a circuit that controls the power MOSFET.

According to the present embodiment, the thickness of the p-type epitaxial layer, which was limited to about 20 μm in FIG. 2 of the conventional example, can be reduced by 40 μm without increasing the diffusion time of the n ⁺ penetrating diffusion layer for a long time at high temperature.
An n ⁺ diffusion layer can penetrate a p-type epitaxial layer having a thickness of m or more, which has the effect of easily realizing high withstand voltage isolation and coexistence with a low on-resistance power MOSFET on the same chip.

Furthermore, since a thick p-type epitaxial layer can be used, even if an antimony-doped n ⁺ buried layer used in a normal bipolar IC is introduced into the circuit portion, there is an effect that a sufficient separation withstand voltage can be secured. .

Further, since the n ⁺ buried layer can be introduced into the circuit section, there is also an effect that the element characteristics of the circuit section can be improved.

According to this embodiment, since the phosphorus buried is formed on the entire surface of the n ⁺ substrate, a photomask is not required, and the cost can be reduced.

Furthermore, since the n-type epitaxial layer is formed on the flat p-type epitaxial layer and the antimony-doped n ⁺ buried layer, the influence of thickness variation due to phosphorus buried side up and resistivity variation due to autodoping are small. ,
It can be formed with high accuracy.

FIG. 4 shows another embodiment of the present invention, in which phosphorus is buried in the power MOS portion using a photomask instead of the entire n ⁺ substrate. As a result, the lateral diffusion of the phosphorus buried layer 51 can be made outside the concave portion provided in the n ⁺ substrate 1, so that the lateral distance required for separating the isolation diffusion layer 6 and the power MOS portion is smaller than that in FIG. There is an effect that can be reduced.

〔The invention's effect〕

According to the present invention, it is possible to penetrate the p-type epitaxial layer twice or more without increasing the high-temperature diffusion time for forming the n ⁺ penetrating diffusion layer in the same time as that of the conventional method, so This has the effect that the withstand voltage between the resistive power MOSFET and the Bi-CMOS circuit can be sufficiently ensured.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to one embodiment of the present invention, and FIG.
3A to 3K are cross-sectional views showing a method of manufacturing the semiconductor device shown in FIG. 1, and FIG. 4 is another embodiment of the present invention. It is sectional drawing of the semiconductor device of an example. DESCRIPTION OF SYMBOLS 1 ... n ^{+ type} silicon substrate, 2 ... oxide film, 3 ... p-type epitaxy layer, 4 ... n-type epitaxy layer, 5 ... n ⁺ buried layer, 6 ... p-type element isolation diffusion layer, 7 ... polysilicon · Gate electrode, 8, 82: p-type diffusion layer, 9: n ^{+ type} diffusion layer, 10: first layer Al electrode, 11: second layer Al electrode, 51: phosphorus buried layer, 83
... p-type well, 101 ... metal electrode, 201 ... interlayer insulating film.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Koichiro Satonaka 111 Nishiyokote-cho, Takasaki-shi, Gunma Co., Ltd. Inside the Takasaki Plant of Hitachi, Ltd. (56) References JP-A-61-285750 (JP, A)

Claims (3)

(57) [Claims] A step of forming a first region of a first conductivity type having a higher concentration than the semiconductor substrate on a main surface of the first conductivity type semiconductor substrate; Forming a recess in the semiconductor substrate; laminating a second conductivity type semiconductor layer thicker than the recess on the entire main surface of the first conductivity type semiconductor substrate having the recess; Forming a thin second conductivity type semiconductor layer on the high concentration first region and a thick second conductivity type semiconductor layer on the concave portion of the semiconductor substrate; By selectively forming the second region of the first conductivity type on the surface of the layer and the surface of the thick second conductivity type semiconductor layer, the first region and the second region formed on the thin second conductivity type semiconductor layer are formed. Forming a through-diffusion layer of the first conductivity type connected to the region; Laminating a first conductivity type semiconductor layer over the entire surface of the semiconductor layer; and a third region of a second conductivity type for element isolation from the surface of the first conductivity type semiconductor layer to the second conductivity type semiconductor layer. Forming a vertical MOS transistor having the semiconductor substrate as a drain in a first conductivity type semiconductor layer portion on the through diffusion layer which is element-isolated by the third region; Forming a lateral MOS transistor in another first conductivity type semiconductor layer portion separated by a region. 2. The semiconductor device according to claim 1, wherein the second region of the first conductivity type is formed using an impurity having a smaller thermal diffusion coefficient than an impurity forming the first region. Production method. 3. The method according to claim 2, wherein the first region of the first conductivity type is formed using phosphorus as an impurity, and the second region is formed using antimony as an impurity.