JP2518855B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

The present invention relates to a high breakdown voltage power IC that coexists with a logic circuit and a small signal circuit, and particularly, a high isolation breakdown voltage and a low on-resistance power MOSFET are provided on the same chip. The present invention relates to a semiconductor device suitable for integration and a manufacturing method thereof.

[Conventional technology]

Conventionally, regarding a semiconductor device in which a high voltage power MOS transistor and a logic circuit or a small signal control circuit coexist,
Electronic Design February 21, 1985, pages 191 to 198 (Electronic Design February21, 1985PP.1
91-198).

[Problems to be solved by the invention]

In the above-mentioned prior art, as shown in FIG. 3, the drain terminal D of the power MOSFET is provided with a deep n-type buried diffusion layer 26 having a high impurity concentration and penetrating through the p-type epitaxial layer 22.
It is taken out from the substrate 21. With this structure, power MOSFET
The withstand voltage of the island surrounded by the p-type epitaxial layer 22 for separating the CMOS logic and the small-signal circuit and the p + type element isolation diffusion layer 27 is mainly limited by the thickness of the p-type epitaxial layer 22. Was there. This is because it cannot be thicker than the depth of the n + type embedded through diffusion layer 26. Therefore, in order not to reduce the effective thickness of the p-type epitaxial layer 22 as much as possible, the conventional shallow n + buried layer has not been provided in the CMOS portion or the small signal circuit portion. Therefore, when the breakdown voltage is increased, there are problems such as an increase in collector series resistance in the low breakdown voltage portion and a decrease in the CMOS latch resistance.

An object of the present invention is to make a high-breakdown-voltage low on-resistance power MOSFET and a control circuit section coexist on the same chip under optimum structural conditions.

[Means for solving problems]

In order to achieve the above object, the semiconductor device of the present invention,
A first epitaxial layer having a conductivity type opposite to that of the semiconductor substrate is formed on the semiconductor substrate of the first conductivity type, and a second epitaxial layer having the same conductivity type as the semiconductor substrate is further formed on the first epitaxial layer. A through-diffusion layer of the first conductivity type which is formed and penetrates through the first epitaxial layer is provided at a required portion of the first epitaxial layer, and a region of the second epitaxial layer on the through-diffusion layer. A semiconductor having a semiconductor substrate as a power supply terminal, and a circuit formed in an island region separated by a diffusion layer of opposite conductivity type provided in the second epitaxial layer and the first epitaxial layer. In the device, the first epitaxial layer has a recess,
The second epitaxial layer of the first conductivity type is formed on the entire surface of the first epitaxial layer having the recess and has a substantially flat surface.
In addition, the through diffusion layer of the first conductivity type is provided in the recess of the first epitaxial layer.

Further, the method of manufacturing a semiconductor device of the present invention comprises: growing a first epitaxial layer of a conductivity type opposite to that of the semiconductor substrate on a semiconductor substrate of a first conductivity type;
After forming a recess in a portion where a transistor having a semiconductor substrate as a power supply terminal is formed by etching, a buried diffusion layer of a first conductivity type is formed in the recess of the first epitaxial layer by using an impurity having a large diffusion coefficient. A step of further forming a second epitaxial layer of the first conductivity type on the entire surface, and then flattening the surface, and a second diffusion layer of the first conductivity type so as to reach the semiconductor substrate. And a step of forming a diffusion layer having a conductivity type opposite to that of the semiconductor substrate reaching the first epitaxial layer from the surface of the epitaxial layer. That is, as shown in FIG. 4, a p-type epitaxial layer 3 is formed on an n + substrate 1, and the p-type epitaxial layer 3 in a portion forming a power MOSFET is etched to form a recess. An n + diffusion layer 51 having a large diffusion coefficient is formed in the concave portion of the jar layer 3, and the n-type epitaxial layer 4 is further grown on the entire surface to planarize the surface, and then the n + diffusion layer 51 formed in the concave portion is formed on the n + substrate 1. The p-type element isolation diffusion layer 6 may be formed so as to reach the side of the n-type epitaxial layer buried in the recess as it reaches.

[Action]

By forming a recess by etching the p-type epitaxial layer in the portion where the power MOSFET is formed, the conventional example can be used without increasing the diffusion time in the high temperature long diffusion process for forming the deep n + buried diffusion layer. Thicker than Fig. 3
The epitaxial layer can be easily penetrated. Therefore, a thick p-type epitaxial layer can be easily obtained,
The punch-through breakdown voltage is improved, and a high element isolation breakdown voltage can be secured.

Also, since a thick p-type epitaxial layer can be used, the necessary punch-through breakdown voltage can be secured even if the n + buried diffusion layer used in a normal bipolar IC is inserted.
It is possible to form a good bipolar device and a CMOS that is resistant to latch-up.

Furthermore, an n + through diffusion layer is formed in the recess by using an impurity having a high diffusion coefficient, for example, phosphorus, so that the n + through-diffusion layer is formed so as to extend into the n-type epitaxial layer embedded in the recess to form the recess. Since the resistance of the n-type epitaxial layer of low impurity concentration made thicker can be made low resistance,
It is possible to prevent the on-resistance of the MOSFET from increasing.

The source electrode of the power MOS portion is a substantially thick Al wiring with a thickness of 3 to μm by using a two-layer wiring,
For the circuit part other than the MOS part, a normal 0.8 to 1 μm thick Al single layer wiring is used. As a result, the power MOS section enables a large current of 5 to several tens of amperes, and the circuit section enables a fine pattern. Further, in the power source line, the ground line, and the like, where the fine pattern is not required in the circuit portion and the mask alignment is not strict, high integration can be achieved by using a thick two-layer wiring.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 7. Here, an IC structure in which a 20A / 60V class n-channel vertical power MOSFET and a Bi-CMOS circuit coexist is taken as an example.

In order to use the 60V class n-channel vertical power MOSFET with low on-resistance, it is necessary to transfer the gate voltage sufficiently high, which is higher than the drain voltage by about 10V. Therefore,
The power MOSFET gate drive circuit must withstand a maximum of 70V or more. FIG. 7 shows, in addition to the vertical power MOSFET, a high breakdown voltage n-channel MOSFET for use in level shift and gate drive, and a high breakdown voltage p of a lateral offset structure.
A channel MOSFET is shown. Since the p-type isolation diffusion layer 6 and the p-type epitaxial layer 3 must be formed on independent islands, respectively, the n-type of 60V class is eventually obtained.
Up to 70 circuits can coexist with a vertical power MOSFET.
A breakdown voltage of V or higher is required. The margin is about 15%, and the isolation withstand voltage of 80V is the design value.

When a high voltage is applied to the drain of the power MOSFET,
The depletion layer extends into the n ^- epitaxial layer 4 and the p-type epitaxial layer 3 in the power MOSFET section. Similarly, when a high voltage is applied to the source of the high breakdown voltage p-channel of the circuit portion, the depletion layer spreads in the n ⁻ epitaxial layer 4 and the p-type epitaxial layer 3. Therefore, in order to secure the isolation breakdown voltage, a thick p-type epitaxial layer 3 that does not connect the depletion layer extending from the n + substrate 1 and the depletion layer extending from the n + buried layer 5, that is, does not punch through is required. Is.

Considering the isolation breakdown voltage of 80 V, a high resistivity of at least 2.5 Ω · cm is used for the p-type epitaxial layer 3. 8
The depletion layer extending into the p-type epitaxial layer 3 when 0 V is applied is about 5 μm in a step junction approximation. n + buried layer 5
Assuming that the diffusion depth is 7 μm, the rise from the n + substrate 1 is also 7 μm, and the minimum required thickness of the p-type epitaxial layer 3 is 24 μm or more. However, since the p-type epitaxial layer 3 is in a substantially pinch-off state, when a substrate current flows in the p-type epitaxial layer 3, a potential drop occurs and a parasitic npn transistor or thyristor operates, causing damage. Sometimes. Therefore, the p-type epitaxial layer 3
The thickness should be 30 μm or more with a sufficient margin.

In FIG. 3 of the conventional example, since the n + buried layer 5 is not included in the circuit portion, the p-type epitaxial layer 22 of 23 μm or more is required. A deep n + through diffusion layer 26 is formed on the p-type layer 22 so that the drain terminal of the power MOSFET section is taken out from the n + substrate 21. In order to obtain a large current and low on-resistance in the power MOSFET, a deep n + through diffusion layer with a high impurity concentration
26 must be formed. Further, in the conventional example, when the separation diffusion layer 27 is formed, it is necessary to suppress an effective decrease in the thickness of the n ^- epitaxial layer 23 due to rising from the n + penetration diffusion layer 26. For example, antimony (Sb) having a small diffusion coefficient is used as the impurity. Even at a depth of about 7 μm, it takes a long time of 1200 ° C. for 15 hours.
It is forced to diffuse at high temperature for 24 hours or more at 00 ℃ for a long time.
Therefore, in the conventional example, even if a method of depositing an impurity with a high diffusion coefficient such as phosphorus on the n + substrate 21 and connecting it to the n + through diffusion layer 26 by raising it, the p-type epitaxial layer having a thickness of at most 20 μm is used. The limit was to penetrate the layers.

On the other hand, in the structure of FIG. 1 of the present invention, the n + through diffusion layer 51 can be formed even if the thick p-type epitaxial layer 3 having a thickness of 30 μm is grown on the n + substrate 1. n +
Before forming the buried layer 5, the p-type epitaxial layer 3 of the power MOSFET section is etched to form a recess having a depth of 15 to 20 μm. By depositing and diffusing n-type impurities of phosphorus 51 and antimony 5 into the recesses, the n-type substrate can be easily connected to the n + substrate 1, and the n-type diffusion layer 6 can be formed when the p-type isolation diffusion layer 6 is formed. By raising the side of 51, it is possible to reduce the resistance of the n-type epitaxial layer 4 which is excessively thick due to the provision of the recess, and it is possible to prevent the on-resistance of the power MOSFET section from increasing. Also, the n + buried layer 5 can be formed in the circuit portion, and a Bi-CMOS circuit having excellent characteristics can be constructed.

As described above, with the structure of the present invention, the island having the sufficiently high isolation breakdown voltage and the island of the power MOSFET can easily coexist.

To obtain a 60V class vertical power MOSFET, n
^- resistivity and the thickness of the epitaxial layer 4 is 0.8Ω · cm, 1
It is about 2 μm. For the n + substrate 1, antimony-doped 0.02 Ωcm or less is used in order to reduce series resistance and rise. In order to obtain a large current of 20 A, it is sufficient to arrange about 5 to 6000 unit cells (about 30 μm pitch) of the MOSFET whose unit is A ₀ shown in FIG.

Since the power MOS section handles a large current, the Al thickness should be 3-4μ.
In order to increase the thickness to m, the Bi-CMOS circuit part, which requires a fine pattern, has a two-layer structure. By using the first layer Al with a thickness of 0.8 to 1 μm, a large current power MOSFET and a highly integrated circuit part can coexist. It is said.

FIG. 2 shows another embodiment of the present invention, in which a higher isolation breakdown voltage is required. In order to penetrate the thick p-type epitaxial layer 3 by the n + diffusion layer, phosphorus is previously deposited to form the n-type buried diffusion layer 52 before the growth of the p-type epitaxial layer 3. As a result, the n + diffusion layer 51 formed in the recess can be easily connected.

An example of a manufacturing method for realizing the structure of FIGS. 1 and 7 of the present invention will be described with reference to FIG. First, the fourth
In FIG. A, p-type 2.5 Ω · cm epitaxial growth of 30 μm is grown on an n-type (100) silicon substrate 1 of 0.02 Ω · cm or less, and then surface oxidation is performed to form an oxide film 2.

In FIG. 9B, the oxide film in the region for forming the vertical power MOSFET is removed by photoetching. At this time, the photomask pattern is a rectangular pattern parallel to the <100> direction. Using the oxide film 2 as an etching mask, for example, at 70 ° C
Anisotropic etching is performed for 30 minutes with a 40 wt% KOH aqueous solution to form a recess having a depth of 15 to 20 μm.

In FIG. 6C, ion implantation is performed at a high concentration of 10 ¹⁵ to 10 ¹⁶ cm ⁻² using the oxide film having phosphorus as the mask in FIG.

In FIG. 6D, an n + buried diffusion layer 5 using antimony as an impurity source is formed in the power MOS recess and the circuit section.

FIG. 4E shows a state in which the n-type epitaxial layer 4 is grown thicker than the depth of the recess after the oxide film is removed. In order to obtain a structure with a flat surface in FIG. 4F from this state, for example, “a method for manufacturing a semiconductor device” previously proposed by the applicant of the present application (Japanese Patent Publication No. 58-43903).
You can use. Alternatively, it may be flattened by using a polishing technique.

In FIG. 4F, the thickness of the n-type epitaxial layer 4 in the portion to be the circuit portion is about 12 μm, and the thickness of the n-type epitaxial layer 4 in the portion to be the power MOS portion is 25 to 30 μm.

In FIG. 4G, after the surface is oxidized, the oxide film is removed by photoetching to form the p-type isolation diffusion layer 6.

In FIG. 4H, a deep n-type diffusion layer 53 is formed. This time,
The p-type isolation diffusion layer 6 reaches the p-type epitaxial layer 3 and
Island separation by joining is completed. Further, the n-type diffusion layer 51 formed in the recess reaches the n + substrate 1 and, at the same time, rises up into the n-type epitaxial layer 4 in the recess, and the effective thickness of the n-type epitaxial layer 4 immediately below the power MOS part. To about 12 μm.

From FIG. 4H onward, vertical power MO
The structure shown in FIGS. 1 and 7 is realized by forming a high breakdown voltage p channel MOS, a Si CMOS circuit, or the like in the portion where S is separated from other islands.

FIG. 5 shows another embodiment of the present invention, in which the n + buried through-diffusion layer 51 to be formed in the recess is inserted into the recess projection after forming the n + buried diffusion layer 5. In the n + buried diffusion layer 51, a high concentration can be easily obtained by using an ordinary phosphorus deposition technique instead of ion implantation of phosphorus, and the armpit can be increased, so that a deep recess can be formed.

FIG. 8 shows a further embodiment of the present invention in which the n + buried through diffusion layer 51 is also applied to the collector portion of the bipolar npn transistor, and at the same time, the deep n + diffusion layer 53 in the power MOS portion of FIG. By omitting, the process is simplified.

FIG. 6 is an example of a manufacturing method for realizing the structure of FIG. 5 of the present invention.

6A and 6B show the same steps as FIGS. 4A and 4B, respectively.

In FIG. 6C, an n + buried diffusion layer 5 using antimony as an impurity source is formed in the recess serving as the power MOS portion and the circuit portion.

In FIG. 4D, the surface oxide film (or the oxide film of about 0.8 μm may be formed when the n + buried diffusion layer 5 is formed) and the oxide film in the recess of the power MOS portion are removed by photoetching to remove phosphorus. Deposit.

FIG. 6E shows a state in which the n-type epitaxial layer 4 is grown thicker than the depth of the recess after the oxide film is removed. In order to obtain the flat surface structure of FIGS. 6E to 6F, for example, the “semiconductor device manufacturing method” previously proposed by the applicant of the present application (Japanese Patent Publication No. 58-43903) may be used. . Alternatively, polishing may be used. In that case, FIG.
It is not necessary to make the rectangular pattern parallel to the <100> direction described in.

In FIG. 6F, the thickness of the n-type epitaxial layer 4 in the circuit portion is about 12 μm, and the thickness of the power MOS portion is 25 to 30 μm.

After the surface is oxidized in FIG. 6G, the oxide film is removed by photoetching to form the p-type isolation diffusion layer 6.

In FIG. 3H, a deep n-type diffusion layer 53 is formed. At this time,
The p-type isolation diffusion layer 6 reaches the p-type epitaxial layer 3 and
Island separation by joining is completed. Further, the n-type through diffusion layer 51 formed in the recess reaches the n + substrate 1 and, at the same time, rises up into the n-type epitaxial layer 4 in the recess, and the power MO
The effective thickness of the n-type epitaxial layer 4 directly under the S part is 12 μm.
Set to about m.

After the same figure H, the vertical power MOS is
, And the other island-separated part has a high withstand voltage p channel.
The structure shown in FIG. 5 is realized by forming MOS, Bi-CMOS, or the like.

〔The invention's effect〕

According to the present invention, the vertical power MOSFET formation portion of the p-type epitaxial layer grown on the n + substrate is etched to form a concave portion, and an impurity having a high diffusion coefficient, for example, phosphorus is diffused into the concave portion. Such a deep n + through diffusion process is unnecessary. Further, since the thick n-type epitaxial layer formed by forming the recess can be canceled by the rise of phosphorus, a thick p-type epitaxial layer can be used without increasing the on-resistance of the power MOS section. . Therefore, the characteristics of the circuit element can be improved by using the n + buried layer also in the circuit portion, and a sufficient isolation voltage can be obtained.

The power MOS part is substantially 3 to 4 μm using the two-layer wiring.
Thick Al so that it can handle a large current of 5 to several 10A,
A fine pattern can be formed in the circuit portion by using the first layer Al having a thickness of 0.8 to 1 μm, and a large current power MOSFET and a highly integrated IC can coexist on the same chip.

[Brief description of drawings]

1 and 7 are sectional views of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view of a semiconductor device according to another embodiment of the present invention, and FIG. 3 is a conventional Bi-CMOS coexisting power. Sectional views of the MOSFET, FIGS. 4A to 4H are process sectional views showing a method for manufacturing the semiconductor device of FIGS. 1 and 7, and FIG. 5 is a semiconductor device of still another embodiment of the present invention. Sectional view of FIG. 6 (A)
(H) is a process sectional view showing the method for manufacturing the semiconductor device of FIG. 5, and FIG. 8 is a sectional view of the semiconductor device showing another embodiment of the present invention. 1 ... n + type silicon substrate, 2 ... oxide film, 201 ... interlayer insulating film, 3 ... p type epitaxial layer, 4 ... n type epitaxial layer, 5 ... n + buried layer, 51,52 ... ... n +
Buried through diffusion layer, 6 ... Diffusion layer for p-type element isolation, 7 ...
… Polysilicon gate electrode, 8,82 …… p-type diffusion layer, 83
... p well, 9 n + diffusion layer, 10 first layer Al
Electrode, 11 …… Second layer Al electrode, 101 …… Metal electrode.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Takeaki Okabe 1-280 Higashi Koigakubo, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Kozo Sakamoto 1-280 Higashi Koigakubo, Kokubunji, Tokyo Hitachi Ltd. Central Research Center

Claims (4)

(57) [Claims] 1. A first epitaxial layer having a conductivity type opposite to that of the semiconductor substrate is formed on a semiconductor substrate of a first conductivity type, and a second epitaxial layer having the same conductivity type as that of the semiconductor substrate is further formed on the first epitaxial layer. A first epitaxial layer is formed and
Is provided with a through diffusion layer of a first conductivity type penetrating the first epitaxial layer in a required portion of the epitaxial layer, and the semiconductor substrate is connected to a power supply terminal in a region of the second epitaxial layer on the through diffusion layer. Forming a transistor, and forming a circuit in an island region separated by a diffusion layer of opposite conductivity type provided in the second epitaxial layer and the first epitaxial layer. The epitaxial layer has a recess, and the second epitaxial layer of the first conductivity type is formed on the entire surface of the first epitaxial layer having the recess and has a substantially flat surface. A semiconductor device, which is formed, and wherein the through diffusion layer of the first conductivity type is provided in the concave portion of the first epitaxial layer. 2. The semiconductor device according to claim 1, wherein the wiring of the transistor having the semiconductor substrate as a power supply terminal has a double-layer electrode structure, and the wiring of the circuit portion has a single-layer electrode structure. 3. The semiconductor device according to claim 1, wherein the transistor having the semiconductor substrate as a power supply terminal is a vertical power MOSFET. 4. A first epitaxial layer of a conductivity type opposite to that of the semiconductor substrate is grown on a semiconductor substrate of a first conductivity type, and a first epitaxial layer is formed.
Of the epitaxial layer, a recess is formed by etching in a portion where a transistor having a semiconductor substrate as a power supply terminal is formed, and then a buried diffusion layer of a first conductivity type is formed using an impurity having a large diffusion coefficient. Of the first conductive type second epitaxial layer and then flattening the surface after the second conductive type second epitaxial layer is formed on the entire surface, and the first conductive type buried diffusion layer is formed on the semiconductor substrate. So as to reach the first epitaxial layer from the surface of the second epitaxial layer, and a step of forming a diffusion layer of opposite conductivity type and a semiconductor substrate, the method of manufacturing a semiconductor device.