JPS648672A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS648672A
JPS648672A JP16232087A JP16232087A JPS648672A JP S648672 A JPS648672 A JP S648672A JP 16232087 A JP16232087 A JP 16232087A JP 16232087 A JP16232087 A JP 16232087A JP S648672 A JPS648672 A JP S648672A
Authority
JP
Japan
Prior art keywords
type
recess
power mosfet
layer
epitaxial layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16232087A
Other languages
Japanese (ja)
Other versions
JP2518855B2 (en
Inventor
Masatoshi Kimura
Koichiro Satonaka
Toyomasa Koda
Takeaki Okabe
Mitsuzo Sakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62162320A priority Critical patent/JP2518855B2/en
Publication of JPS648672A publication Critical patent/JPS648672A/en
Application granted granted Critical
Publication of JP2518855B2 publication Critical patent/JP2518855B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To easily obtain a thick P-type epitaxial layer, to improve punch- through breakdown strength, and to ensure high breakdown strength of element isolation by etching the epitaxial layer of a section for forming a power MOSFET to form a recess. CONSTITUTION:Before an N<+> type buried layer 5 is formed, a P-type epitaxial layer 3 of a power MOSFET is etched to form a recess having 15-20mum of depth. N-type impurities of phosphorus 51 and antimony 5 are deposited in the recess, diffused to be easily connected to an N+ type substrate 1, the resistance of an N-type epitaxial layer 4 excessively thickened due to the recess can be reduced by the side rise of an N-type diffused layer 51 at the time of forming a dispersively diffused layer 6 to prevent the ON resistance of the power MOSFET from increasing. An N<+> type buried layer 5 can be also formed in a circuit, thereby forming a Bi-CMOS circuit having preferable characteristics. Thus, an island having sufficiently high breakdown strength of isolation and an island of the power MOSFET can coexist.
JP62162320A 1987-07-01 1987-07-01 Semiconductor device and manufacturing method thereof Expired - Fee Related JP2518855B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62162320A JP2518855B2 (en) 1987-07-01 1987-07-01 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62162320A JP2518855B2 (en) 1987-07-01 1987-07-01 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPS648672A true JPS648672A (en) 1989-01-12
JP2518855B2 JP2518855B2 (en) 1996-07-31

Family

ID=15752289

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62162320A Expired - Fee Related JP2518855B2 (en) 1987-07-01 1987-07-01 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP2518855B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100487412B1 (en) * 2002-09-24 2005-05-03 매그나칩 반도체 유한회사 Method for fabricating of semiconductor device
US9685524B2 (en) 2005-03-11 2017-06-20 Vishay-Siliconix Narrow semiconductor trench structure
US9887266B2 (en) 2006-03-21 2018-02-06 Vishay-Siliconix Ultra-low drain-source resistance power MOSFET
US10354920B2 (en) 2011-11-22 2019-07-16 Taiwan Semiconductor Manufacturing Company Methods and apparatus for MOS capacitors in replacement gate process

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100487412B1 (en) * 2002-09-24 2005-05-03 매그나칩 반도체 유한회사 Method for fabricating of semiconductor device
US9685524B2 (en) 2005-03-11 2017-06-20 Vishay-Siliconix Narrow semiconductor trench structure
US9887266B2 (en) 2006-03-21 2018-02-06 Vishay-Siliconix Ultra-low drain-source resistance power MOSFET
US10354920B2 (en) 2011-11-22 2019-07-16 Taiwan Semiconductor Manufacturing Company Methods and apparatus for MOS capacitors in replacement gate process
US10720361B2 (en) 2011-11-22 2020-07-21 Taiwan Semiconductor Manufacturing Company Methods and apparatus for MOS capacitors in replacement gate process

Also Published As

Publication number Publication date
JP2518855B2 (en) 1996-07-31

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees