JPS6251012B2 - - Google Patents
Info
- Publication number
- JPS6251012B2 JPS6251012B2 JP54053028A JP5302879A JPS6251012B2 JP S6251012 B2 JPS6251012 B2 JP S6251012B2 JP 54053028 A JP54053028 A JP 54053028A JP 5302879 A JP5302879 A JP 5302879A JP S6251012 B2 JPS6251012 B2 JP S6251012B2
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- clock
- multiplexed signal
- pulse
- staff
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000004904 shortening Methods 0.000 claims description 2
- 238000012544 monitoring process Methods 0.000 description 6
- 230000001360 synchronised effect Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000000284 extract Substances 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
- H04J3/073—Bit stuffing, e.g. PDH
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Time-Division Multiplex Systems (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5302879A JPS55145454A (en) | 1979-04-28 | 1979-04-28 | Stuff control circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5302879A JPS55145454A (en) | 1979-04-28 | 1979-04-28 | Stuff control circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55145454A JPS55145454A (en) | 1980-11-13 |
JPS6251012B2 true JPS6251012B2 (US07534539-20090519-C00280.png) | 1987-10-28 |
Family
ID=12931428
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5302879A Granted JPS55145454A (en) | 1979-04-28 | 1979-04-28 | Stuff control circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55145454A (US07534539-20090519-C00280.png) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01161104U (US07534539-20090519-C00280.png) * | 1988-04-30 | 1989-11-09 |
-
1979
- 1979-04-28 JP JP5302879A patent/JPS55145454A/ja active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01161104U (US07534539-20090519-C00280.png) * | 1988-04-30 | 1989-11-09 |
Also Published As
Publication number | Publication date |
---|---|
JPS55145454A (en) | 1980-11-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4973860A (en) | Circuit for synchronizing an asynchronous input signal to a high frequency clock | |
US3982195A (en) | Method and apparatus for decoding diphase signals | |
JP3084151B2 (ja) | 情報処理システム | |
JPH0642663B2 (ja) | ディジタル通信方式の中間中継局 | |
JPS594900B2 (ja) | クロック再生回路 | |
GB1481849A (en) | Digital code transmission systems | |
JPS6214546A (ja) | 準同期バツフア制御方式 | |
JPS5812776B2 (ja) | デイジタルシンゴウノソクドヘンカンカイロ | |
US4804928A (en) | Phase-frequency compare circuit for phase lock loop | |
JPS6251012B2 (US07534539-20090519-C00280.png) | ||
US4489421A (en) | Digital message transmission system employing pulse stuffing and having two plesiochronic sampling clocks | |
US3761625A (en) | Digital method and means for frequency shift keying | |
US3692941A (en) | Data exchange and coupling apparatus | |
JPS62102648A (ja) | Qam信号からの搬送波再生用捕捉引込回路 | |
JPS5923496B2 (ja) | タイミング抽出方式 | |
CA1254270A (en) | Phase-locked loop | |
JP2743846B2 (ja) | 位相同期回路 | |
JPS5819056A (ja) | クロツク再生回路 | |
JP3122801B2 (ja) | ポインタ処理回路 | |
SU1053317A2 (ru) | Устройство дл асинхронного сопр жени каналов св зи | |
JPS58198937A (ja) | デイジタルデ−タ伝送の同期補正方式 | |
JPS59835Y2 (ja) | ディジタル通信系の通信方式の変換装置 | |
JPH0834462B2 (ja) | フレームアライナ装置 | |
JP2522259B2 (ja) | デイジタル型位相同期方法 | |
JPS6350896B2 (US07534539-20090519-C00280.png) |