JPS6250063B2 - - Google Patents

Info

Publication number
JPS6250063B2
JPS6250063B2 JP4326082A JP4326082A JPS6250063B2 JP S6250063 B2 JPS6250063 B2 JP S6250063B2 JP 4326082 A JP4326082 A JP 4326082A JP 4326082 A JP4326082 A JP 4326082A JP S6250063 B2 JPS6250063 B2 JP S6250063B2
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
substrates
board
present
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP4326082A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58159361A (ja
Inventor
Yoshio Miura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Denki Co Ltd
Original Assignee
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Denki Co Ltd filed Critical Sanyo Denki Co Ltd
Priority to JP4326082A priority Critical patent/JPS58159361A/ja
Publication of JPS58159361A publication Critical patent/JPS58159361A/ja
Publication of JPS6250063B2 publication Critical patent/JPS6250063B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385Assembly of a plurality of insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/144Stacked arrangements of planar printed circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3405Edge mounted components, e.g. terminals

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP4326082A 1982-03-17 1982-03-17 多層混成集積回路装置 Granted JPS58159361A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4326082A JPS58159361A (ja) 1982-03-17 1982-03-17 多層混成集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4326082A JPS58159361A (ja) 1982-03-17 1982-03-17 多層混成集積回路装置

Publications (2)

Publication Number Publication Date
JPS58159361A JPS58159361A (ja) 1983-09-21
JPS6250063B2 true JPS6250063B2 (US07709020-20100504-C00041.png) 1987-10-22

Family

ID=12658876

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4326082A Granted JPS58159361A (ja) 1982-03-17 1982-03-17 多層混成集積回路装置

Country Status (1)

Country Link
JP (1) JPS58159361A (US07709020-20100504-C00041.png)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862322A (en) * 1988-05-02 1989-08-29 Bickford Harry R Double electronic device structure having beam leads solderlessly bonded between contact locations on each device and projecting outwardly from therebetween
KR920702545A (ko) * 1990-06-26 1992-09-04 아이자와 스스무 반도체 장치 및 그 제조 방법
US5296737A (en) * 1990-09-06 1994-03-22 Hitachi, Ltd. Semiconductor device with a plurality of face to face chips
JPH0685161A (ja) * 1992-09-07 1994-03-25 Hitachi Ltd 高密度実装型半導体装置
US5479051A (en) * 1992-10-09 1995-12-26 Fujitsu Limited Semiconductor device having a plurality of semiconductor chips
WO2019012679A1 (ja) * 2017-07-14 2019-01-17 新電元工業株式会社 電子モジュール

Also Published As

Publication number Publication date
JPS58159361A (ja) 1983-09-21

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