JPS6249540A - 浮動小数点除算方式 - Google Patents
浮動小数点除算方式Info
- Publication number
- JPS6249540A JPS6249540A JP60190632A JP19063285A JPS6249540A JP S6249540 A JPS6249540 A JP S6249540A JP 60190632 A JP60190632 A JP 60190632A JP 19063285 A JP19063285 A JP 19063285A JP S6249540 A JPS6249540 A JP S6249540A
- Authority
- JP
- Japan
- Prior art keywords
- exponent part
- value
- exponent
- bit
- extended
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60190632A JPS6249540A (ja) | 1985-08-29 | 1985-08-29 | 浮動小数点除算方式 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60190632A JPS6249540A (ja) | 1985-08-29 | 1985-08-29 | 浮動小数点除算方式 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6249540A true JPS6249540A (ja) | 1987-03-04 |
JPH0467652B2 JPH0467652B2 (enrdf_load_stackoverflow) | 1992-10-29 |
Family
ID=16261297
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60190632A Granted JPS6249540A (ja) | 1985-08-29 | 1985-08-29 | 浮動小数点除算方式 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6249540A (enrdf_load_stackoverflow) |
-
1985
- 1985-08-29 JP JP60190632A patent/JPS6249540A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPH0467652B2 (enrdf_load_stackoverflow) | 1992-10-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3076046B2 (ja) | 例外検出回路 | |
EP0416308A2 (en) | Rectangular array signed digit multiplier | |
JPH0520028A (ja) | 加減算のための浮動小数点演算装置の仮数部処理回路 | |
JPH0343645B2 (enrdf_load_stackoverflow) | ||
JP2511527B2 (ja) | 浮動小数点演算器 | |
JPS59226944A (ja) | 浮動小数点デ−タ加減算方式 | |
JPS6249540A (ja) | 浮動小数点除算方式 | |
CN111290790B (zh) | 一种定点转浮点的转换装置 | |
Vassiliadis et al. | Brief communication Condition code predictor for fixed-point arithmetic units | |
US7003540B2 (en) | Floating point multiplier for delimited operands | |
JPS63158626A (ja) | 演算処理装置 | |
JPS61282928A (ja) | 浮動小数点演算装置 | |
US5689721A (en) | Detecting overflow conditions for negative quotients in nonrestoring two's complement division | |
JPS58186840A (ja) | デ−タ処理装置 | |
JPS6154537A (ja) | 浮動小数点加減算方式 | |
JPS6148038A (ja) | 加算器の零検出方式 | |
JPH07104777B2 (ja) | 浮動小数点加減算装置 | |
JP3370688B2 (ja) | 加算器のフラグ生成回路 | |
JPS60235241A (ja) | 浮動小数点加算回路 | |
JPH07134645A (ja) | 情報処理用条件コード生成装置 | |
JPH01128129A (ja) | 浮動小数点加減算装置 | |
JPH03245226A (ja) | 浮動小数点乗算装置 | |
JPH03217938A (ja) | 浮動小数点丸め正規化装置 | |
JPH0370029A (ja) | 浮動小数点演算装置 | |
JPS60235239A (ja) | 浮動小数点加算回路 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |