JPS624867B2 - - Google Patents

Info

Publication number
JPS624867B2
JPS624867B2 JP57176499A JP17649982A JPS624867B2 JP S624867 B2 JPS624867 B2 JP S624867B2 JP 57176499 A JP57176499 A JP 57176499A JP 17649982 A JP17649982 A JP 17649982A JP S624867 B2 JPS624867 B2 JP S624867B2
Authority
JP
Japan
Prior art keywords
layer
polysilicon
silicon
silicon dioxide
sub
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57176499A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58118155A (ja
Inventor
Homero De Ra Moneda Furanshisuko
Chaaruzu Dotsukaatei Robaato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS58118155A publication Critical patent/JPS58118155A/ja
Publication of JPS624867B2 publication Critical patent/JPS624867B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H10W10/13—
    • H10D64/01328—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H10D84/0142—Manufacturing their gate conductors the gate conductors having different shapes or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10W10/0126—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)
  • Semiconductor Memories (AREA)
JP57176499A 1981-12-30 1982-10-08 半導体装置の製造方法 Granted JPS58118155A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US335953 1981-12-30
US06/335,953 US4445267A (en) 1981-12-30 1981-12-30 MOSFET Structure and process to form micrometer long source/drain spacing

Publications (2)

Publication Number Publication Date
JPS58118155A JPS58118155A (ja) 1983-07-14
JPS624867B2 true JPS624867B2 (index.php) 1987-02-02

Family

ID=23313943

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57176499A Granted JPS58118155A (ja) 1981-12-30 1982-10-08 半導体装置の製造方法

Country Status (4)

Country Link
US (1) US4445267A (index.php)
EP (1) EP0083783B1 (index.php)
JP (1) JPS58118155A (index.php)
DE (1) DE3277664D1 (index.php)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0215987U (index.php) * 1988-07-19 1990-02-01

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4546535A (en) * 1983-12-12 1985-10-15 International Business Machines Corporation Method of making submicron FET structure
US4551906A (en) * 1983-12-12 1985-11-12 International Business Machines Corporation Method for making self-aligned lateral bipolar transistors
US4636834A (en) * 1983-12-12 1987-01-13 International Business Machines Corporation Submicron FET structure and method of making
US4555842A (en) * 1984-03-19 1985-12-03 At&T Bell Laboratories Method of fabricating VLSI CMOS devices having complementary threshold voltages
US4658496A (en) * 1984-11-29 1987-04-21 Siemens Aktiengesellschaft Method for manufacturing VLSI MOS-transistor circuits
US5257095A (en) * 1985-12-04 1993-10-26 Advanced Micro Devices, Inc. Common geometry high voltage tolerant long channel and high speed short channel field effect transistors
DE3602461A1 (de) * 1986-01-28 1987-07-30 Telefunken Electronic Gmbh Verfahren zum herstellen eines sperrschicht-feldeffekttransistors
DE3682395D1 (de) * 1986-03-27 1991-12-12 Ibm Verfahren zur herstellung von seitenstrukturen.
US4689869A (en) * 1986-04-07 1987-09-01 International Business Machines Corporation Fabrication of insulated gate gallium arsenide FET with self-aligned source/drain and submicron channel length
JPH0766968B2 (ja) * 1987-08-24 1995-07-19 株式会社日立製作所 半導体装置及びその製造方法
US5179034A (en) * 1987-08-24 1993-01-12 Hitachi, Ltd. Method for fabricating insulated gate semiconductor device
EP0313683A1 (en) * 1987-10-30 1989-05-03 International Business Machines Corporation Method for fabricating a semiconductor integrated circuit structure having a submicrometer length device element
EP0416141A1 (de) * 1989-09-04 1991-03-13 Siemens Aktiengesellschaft Verfahren zur Herstellung eines FET mit asymmetrisch angeordnetem Gate-Bereich
US5153145A (en) * 1989-10-17 1992-10-06 At&T Bell Laboratories Fet with gate spacer
JP2673380B2 (ja) * 1990-02-20 1997-11-05 三菱電機株式会社 プラズマエッチングの方法
US5273921A (en) * 1991-12-27 1993-12-28 Purdue Research Foundation Methods for fabricating a dual-gated semiconductor-on-insulator field effect transistor
US5470801A (en) * 1993-06-28 1995-11-28 Lsi Logic Corporation Low dielectric constant insulation layer for integrated circuit structure and method of making same
US6184083B1 (en) * 1997-06-30 2001-02-06 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
EP1100128B1 (en) * 1998-06-30 2009-04-15 Sharp Kabushiki Kaisha Method of manufacture of a semiconductor device
US5981363A (en) * 1998-11-17 1999-11-09 Gardner; Mark I. Method and apparatus for high performance transistor devices
CN1106099C (zh) * 1999-06-14 2003-04-16 林昌鑫 多媒体数据的播放装置与方法
HK1048888A1 (zh) 1999-09-10 2003-04-17 Oerlikon Usa Inc. 磁极制备的方法和设备
US6547975B1 (en) 1999-10-29 2003-04-15 Unaxis Usa Inc. Magnetic pole fabrication process and device
US20110003466A1 (en) * 2009-07-02 2011-01-06 Innovalight, Inc. Methods of forming a multi-doped junction with porous silicon
US8513104B2 (en) 2009-07-02 2013-08-20 Innovalight, Inc. Methods of forming a floating junction on a solar cell with a particle masking layer
US20110183504A1 (en) * 2010-01-25 2011-07-28 Innovalight, Inc. Methods of forming a dual-doped emitter on a substrate with an inline diffusion apparatus
US8163587B2 (en) 2009-07-02 2012-04-24 Innovalight, Inc. Methods of using a silicon nanoparticle fluid to control in situ a set of dopant diffusion profiles
US8420517B2 (en) * 2009-07-02 2013-04-16 Innovalight, Inc. Methods of forming a multi-doped junction with silicon-containing particles

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4062699A (en) * 1976-02-20 1977-12-13 Western Digital Corporation Method for fabricating diffusion self-aligned short channel MOS device
US4145459A (en) * 1978-02-02 1979-03-20 Rca Corporation Method of making a short gate field effect transistor
US4209349A (en) * 1978-11-03 1980-06-24 International Business Machines Corporation Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching
US4256514A (en) * 1978-11-03 1981-03-17 International Business Machines Corporation Method for forming a narrow dimensioned region on a body
US4234362A (en) * 1978-11-03 1980-11-18 International Business Machines Corporation Method for forming an insulator between layers of conductive material
US4209350A (en) * 1978-11-03 1980-06-24 International Business Machines Corporation Method for forming diffusions having narrow dimensions utilizing reactive ion etching
US4201603A (en) * 1978-12-04 1980-05-06 Rca Corporation Method of fabricating improved short channel MOS devices utilizing selective etching and counterdoping of polycrystalline silicon
US4244001A (en) * 1979-09-28 1981-01-06 Rca Corporation Fabrication of an integrated injection logic device with narrow basewidth
US4359816A (en) * 1980-07-08 1982-11-23 International Business Machines Corporation Self-aligned metal process for field effect transistor integrated circuits
US4358340A (en) * 1980-07-14 1982-11-09 Texas Instruments Incorporated Submicron patterning without using submicron lithographic technique
US4334348A (en) * 1980-07-21 1982-06-15 Data General Corporation Retro-etch process for forming gate electrodes of MOS integrated circuits
US4324038A (en) * 1980-11-24 1982-04-13 Bell Telephone Laboratories, Incorporated Method of fabricating MOS field effect transistors
US4366613A (en) * 1980-12-17 1983-01-04 Ibm Corporation Method of fabricating an MOS dynamic RAM with lightly doped drain
US4375713A (en) * 1980-12-22 1983-03-08 Textron, Inc. Clasp for adjusting bracelet length

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0215987U (index.php) * 1988-07-19 1990-02-01

Also Published As

Publication number Publication date
US4445267A (en) 1984-05-01
DE3277664D1 (en) 1987-12-17
EP0083783A3 (en) 1985-01-23
EP0083783B1 (en) 1987-11-11
EP0083783A2 (en) 1983-07-20
JPS58118155A (ja) 1983-07-14

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