JPS6244463U - - Google Patents
Info
- Publication number
- JPS6244463U JPS6244463U JP13504585U JP13504585U JPS6244463U JP S6244463 U JPS6244463 U JP S6244463U JP 13504585 U JP13504585 U JP 13504585U JP 13504585 U JP13504585 U JP 13504585U JP S6244463 U JPS6244463 U JP S6244463U
- Authority
- JP
- Japan
- Prior art keywords
- solder
- resistance layer
- circuit board
- pattern
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- 230000008030 elimination Effects 0.000 claims 1
- 238000003379 elimination reaction Methods 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
第１図は本考案の実施例であつて、電子部品と
配線基板との係合状態を示す配線基板の縦断面図
、第２図は第１図の平面図、第３図は電子部品と
従来構造の配線基板との係合状態を示す配線基板
の縦断面図である。
１……絶縁基板、２……導電体パターン、３…
…ダミーパターン、４……半田抵抗層、５……半
田、７……電子部品、８……リード端子、９……
ランド、１０……空間部。
FIG. 1 is a longitudinal cross-sectional view of a wiring board showing an engagement state between an electronic component and a wiring board, FIG. 2 is a plan view of FIG. 1, and FIG. 3 is an embodiment of the present invention. FIG. 2 is a longitudinal cross-sectional view of a wiring board showing a state of engagement with a wiring board of a conventional structure. 1... Insulating substrate, 2... Conductor pattern, 3...
...Dummy pattern, 4...Solder resistance layer, 5...Solder, 7...Electronic component, 8...Lead terminal, 9...
Land, 10... Space Department.
Claims (1)
半田抵抗層を形成し、半田抵抗層の非形成部たる
ランドと電子部品のリード端子とを半田により接
続するものにおいて、各導電体パターン形成部の
の間の空間部に対して凹所解消用のダミーパター
ンを形成し、半田の橋絡を防止するよう構成した
ことを特徴とする回路基板。 (2) 実用新案登録請求の範囲第(1)項記載におい
て、導電体パターンとダミーパターンとを同一材
料により構成したことを特徴とする回路基板。[Scope of Claim for Utility Model Registration] (1) A solder resistance layer is formed on an insulating substrate on which a conductive pattern is formed, and the land, which is the part where the solder resistance layer is not formed, is connected by solder to the lead terminal of an electronic component. 1. A circuit board according to claim 1, characterized in that a dummy pattern for recess elimination is formed in a space between each conductor pattern forming part to prevent solder bridging. (2) A circuit board as set forth in claim (1) of the utility model registration, characterized in that the conductive pattern and the dummy pattern are made of the same material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13504585U JPS6244463U (en) | 1985-09-05 | 1985-09-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13504585U JPS6244463U (en) | 1985-09-05 | 1985-09-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6244463U true JPS6244463U (en) | 1987-03-17 |
Family
ID=31036854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13504585U Pending JPS6244463U (en) | 1985-09-05 | 1985-09-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6244463U (en) |
-
1985
- 1985-09-05 JP JP13504585U patent/JPS6244463U/ja active Pending
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