JPS6243539B2 - - Google Patents
Info
- Publication number
- JPS6243539B2 JPS6243539B2 JP5115480A JP5115480A JPS6243539B2 JP S6243539 B2 JPS6243539 B2 JP S6243539B2 JP 5115480 A JP5115480 A JP 5115480A JP 5115480 A JP5115480 A JP 5115480A JP S6243539 B2 JPS6243539 B2 JP S6243539B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- circuit board
- insulating layer
- conductor
- carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004020 conductor Substances 0.000 claims description 19
- 239000004593 Epoxy Substances 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 4
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 claims description 2
- 239000000919 ceramic Substances 0.000 claims description 2
- 239000000853 adhesive Substances 0.000 claims 2
- 230000001070 adhesive effect Effects 0.000 claims 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims 1
- 125000006850 spacer group Chemical group 0.000 description 11
- 239000000463 material Substances 0.000 description 6
- 238000003475 lamination Methods 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 1
- 239000011162 core material Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000012768 molten material Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5115480A JPS56146264A (en) | 1980-04-14 | 1980-04-14 | Carrier for equipment of chip |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5115480A JPS56146264A (en) | 1980-04-14 | 1980-04-14 | Carrier for equipment of chip |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56146264A JPS56146264A (en) | 1981-11-13 |
JPS6243539B2 true JPS6243539B2 (fr) | 1987-09-14 |
Family
ID=12878897
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5115480A Granted JPS56146264A (en) | 1980-04-14 | 1980-04-14 | Carrier for equipment of chip |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56146264A (fr) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0334444U (fr) * | 1989-08-11 | 1991-04-04 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3629348B2 (ja) * | 1997-04-16 | 2005-03-16 | 新光電気工業株式会社 | 配線基板 |
-
1980
- 1980-04-14 JP JP5115480A patent/JPS56146264A/ja active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0334444U (fr) * | 1989-08-11 | 1991-04-04 |
Also Published As
Publication number | Publication date |
---|---|
JPS56146264A (en) | 1981-11-13 |
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