JPS6243338B2 - - Google Patents
Info
- Publication number
- JPS6243338B2 JPS6243338B2 JP56142528A JP14252881A JPS6243338B2 JP S6243338 B2 JPS6243338 B2 JP S6243338B2 JP 56142528 A JP56142528 A JP 56142528A JP 14252881 A JP14252881 A JP 14252881A JP S6243338 B2 JPS6243338 B2 JP S6243338B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- bonding
- wiring
- pure
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 14
- 229910052782 aluminium Inorganic materials 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/023—Redistribution layers [RDL] for bonding areas
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/05073—Single internal layer
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- Engineering & Computer Science (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
本発明は、半導体装置の高安定電極・配線に関
するものである。
するものである。
従来、半導体装置の電極・配線には、純Al又
はSi入りAlが用いられていた。しかし、純Al、Si
入りAlは、Siに対するエレクトロマイグレーシヨ
ン耐量が小さく、高電流密度の電流を流すと、電
極と半導体のコンタクト抵抗が増大する欠点があ
つた。
はSi入りAlが用いられていた。しかし、純Al、Si
入りAlは、Siに対するエレクトロマイグレーシヨ
ン耐量が小さく、高電流密度の電流を流すと、電
極と半導体のコンタクト抵抗が増大する欠点があ
つた。
本発明は、これらの欠点を除去するために、半
導体とのコンタクトをとる電極及び配線にはCu
入りAlを用い、ボンデイングパツド部にボンデ
イングの安定性にすぐれた純Al又はSi入りAlを
用いたもので、その目的は高精度を要求される半
導体装置(例えばアナログIC)の高安定電極・
配線を実現することにある。
導体とのコンタクトをとる電極及び配線にはCu
入りAlを用い、ボンデイングパツド部にボンデ
イングの安定性にすぐれた純Al又はSi入りAlを
用いたもので、その目的は高精度を要求される半
導体装置(例えばアナログIC)の高安定電極・
配線を実現することにある。
以下、本発明を実施例によつて詳細に説明す
る。
る。
第1図は本発明の実施例の構造を示した断面図
である。図において、1は半導体基板(Si基
板)、2は不純物(例えばP、As、B等)を拡散
した拡散層、3は窓明けされた絶縁物(例えば厚
さ0.1〜0.5μmのSiO2膜)、4はCu入りAl層(Cu
の含有率0.5〜12%)で形成(例えば蒸着、スパ
ツタ等により厚さ1〜2μmに堆積させ、その後
400〜500℃の熱処理を約10分間施こして安定化す
る。)された電極・配線であり、拡散層2とコン
タクト5で接触している。6はボンデイングの安
定性にすぐれた純Al層又はSi入りAl層(Siの含有
率1.5〜4%、厚さは例えば1〜2μm)で、ボ
ンデイングワイヤ7(例えばAl、Au線)がここ
にボンデイング(熱圧着又は超音波ボンデイング
等により)される。
である。図において、1は半導体基板(Si基
板)、2は不純物(例えばP、As、B等)を拡散
した拡散層、3は窓明けされた絶縁物(例えば厚
さ0.1〜0.5μmのSiO2膜)、4はCu入りAl層(Cu
の含有率0.5〜12%)で形成(例えば蒸着、スパ
ツタ等により厚さ1〜2μmに堆積させ、その後
400〜500℃の熱処理を約10分間施こして安定化す
る。)された電極・配線であり、拡散層2とコン
タクト5で接触している。6はボンデイングの安
定性にすぐれた純Al層又はSi入りAl層(Siの含有
率1.5〜4%、厚さは例えば1〜2μm)で、ボ
ンデイングワイヤ7(例えばAl、Au線)がここ
にボンデイング(熱圧着又は超音波ボンデイング
等により)される。
このように構成すると、ボンデイングは純Al
又はSi入りAlによつて安定になり、Cu入りAl電
極を用いたコンタクトでは、以下に述べるように
Si入りAl等を用いた場合に比べコンタクト抵抗の
増大が少なく高安定な電極となる。
又はSi入りAlによつて安定になり、Cu入りAl電
極を用いたコンタクトでは、以下に述べるように
Si入りAl等を用いた場合に比べコンタクト抵抗の
増大が少なく高安定な電極となる。
第2図は本発明の効果を説明するためのグラフ
であり、10Ωの拡散抵抗体の電極として、従来の
Si入りAlを用いた場合と本発明のCu入りAlを用
いた場合の高温通電試験における抵抗値の経時変
動を示す。この抵抗体(例えばアナログICの高
精度拡散抵抗として用いる。)には、0.5%の精度
が要求されているが、図から明らかなように、Si
入りAlに比べCu入りAlを電極として用いた方が
安定である。
であり、10Ωの拡散抵抗体の電極として、従来の
Si入りAlを用いた場合と本発明のCu入りAlを用
いた場合の高温通電試験における抵抗値の経時変
動を示す。この抵抗体(例えばアナログICの高
精度拡散抵抗として用いる。)には、0.5%の精度
が要求されているが、図から明らかなように、Si
入りAlに比べCu入りAlを電極として用いた方が
安定である。
この理由は、Cu入りAlがSiに対するエレクト
ロマイグレーシヨン耐量にすぐれているため、半
導体基板からCu入りAlに溶け込んだSiが移動せ
ずコンタクト部分ですぐにAl中の飽和濃度に達
し、Cu入りAl中にSiが溶け込む反応が止まるか
らである。これに対して、Si入りAlはエレクトロ
マイグレーシヨン耐量が小さいため、コンタクト
近傍のSiがエレクトロマイグレーシヨンにより持
ち去られ、Al中にSiが溶け込む反応が続き、半導
体基板のコンタクト部分にエツチピツト、ボイド
等が形成されコンタクト抵抗が増大することによ
る。
ロマイグレーシヨン耐量にすぐれているため、半
導体基板からCu入りAlに溶け込んだSiが移動せ
ずコンタクト部分ですぐにAl中の飽和濃度に達
し、Cu入りAl中にSiが溶け込む反応が止まるか
らである。これに対して、Si入りAlはエレクトロ
マイグレーシヨン耐量が小さいため、コンタクト
近傍のSiがエレクトロマイグレーシヨンにより持
ち去られ、Al中にSiが溶け込む反応が続き、半導
体基板のコンタクト部分にエツチピツト、ボイド
等が形成されコンタクト抵抗が増大することによ
る。
Cu入りAlは以上のように半導体とのコンタク
ト抵抗の安定性にはすぐれるが、膜質が固くボン
デイングの安定性が悪い(付きにくかつたり接着
強度が弱い等)欠点がある。そのため、ボンデイ
ング部にボンデイングの安定性にすぐれた純Al
又はSi入りAlを用いる必要がある。
ト抵抗の安定性にはすぐれるが、膜質が固くボン
デイングの安定性が悪い(付きにくかつたり接着
強度が弱い等)欠点がある。そのため、ボンデイ
ング部にボンデイングの安定性にすぐれた純Al
又はSi入りAlを用いる必要がある。
第3図は本発明のもう一つの実施例の構造を示
した断面図である。図において、前出のものと同
一符号のものは同一又は均等部分を示すものとす
る。この実施例は、第1図の実施例におけるCu
入りAl層4と、純Al又はSi入りAl層6の中間に
例えばMo、W、Ti等のメタル層8(例えば厚さ
0.1〜1.0μm)を入れたものである。このメタル
層8は、ボンデイング前に、保護膜の形成等によ
り400℃程度の高温にさらされる際に、Cu入りAl
層4中のCuが純Al又はSi入りAl層6に拡散する
のを防止する役割をはたす。既に述べたように、
Cu入りAl層は、膜質が固く、ボンデイングにお
いて付きにくかつたり、接着強度が弱いので、
Cuが拡散して純Al又はSi入りAl層の表面にまで
分布すると、ボンデイングがうまくいかなくな
る。メタル層8は、これを防止してボンデイング
の安定性を確保する。
した断面図である。図において、前出のものと同
一符号のものは同一又は均等部分を示すものとす
る。この実施例は、第1図の実施例におけるCu
入りAl層4と、純Al又はSi入りAl層6の中間に
例えばMo、W、Ti等のメタル層8(例えば厚さ
0.1〜1.0μm)を入れたものである。このメタル
層8は、ボンデイング前に、保護膜の形成等によ
り400℃程度の高温にさらされる際に、Cu入りAl
層4中のCuが純Al又はSi入りAl層6に拡散する
のを防止する役割をはたす。既に述べたように、
Cu入りAl層は、膜質が固く、ボンデイングにお
いて付きにくかつたり、接着強度が弱いので、
Cuが拡散して純Al又はSi入りAl層の表面にまで
分布すると、ボンデイングがうまくいかなくな
る。メタル層8は、これを防止してボンデイング
の安定性を確保する。
以上説明したように、本発明によれば、半導体
と電極のコンタクト部分におけるコンタクト抵抗
の増大(経時変化)がほとんど無く、かつボンデ
イングの安定性にすぐれた電極・配線が得られ
る。
と電極のコンタクト部分におけるコンタクト抵抗
の増大(経時変化)がほとんど無く、かつボンデ
イングの安定性にすぐれた電極・配線が得られ
る。
また、電極・配線形成後に熱処理が加わる場合
でも、メタル層の挿入により、ボンデイングの安
定性は維持され、高安定な電極・配線となる。
でも、メタル層の挿入により、ボンデイングの安
定性は維持され、高安定な電極・配線となる。
第1図及び第3図はそれぞれ本発明の実施例の
構造を示した断面図、第2図は本発明の効果を説
明するためのグラフである。 1…半導体基板、2…拡散層、3…絶縁物、4
…Cu入りAl層、5…半導体と電極のコンタク
ト、6…純Al又はSi入りAl層、7…ボンデイン
グワイヤ、8…メタル層。
構造を示した断面図、第2図は本発明の効果を説
明するためのグラフである。 1…半導体基板、2…拡散層、3…絶縁物、4
…Cu入りAl層、5…半導体と電極のコンタク
ト、6…純Al又はSi入りAl層、7…ボンデイン
グワイヤ、8…メタル層。
Claims (1)
- 1 半導体基板とのコンタクトをとる電極及び配
線にCu入りAl層を用い、ボンデイングパツド部
は該Cu入りAl層上にCuの拡散を阻止するメタル
層と該メタル層上に純Al層又はSi入りAl層を備
えて構成したことを特徴とする半導体装置の電
極・配線。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56142528A JPS5844730A (ja) | 1981-09-11 | 1981-09-11 | 半導体装置の電極・配線 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56142528A JPS5844730A (ja) | 1981-09-11 | 1981-09-11 | 半導体装置の電極・配線 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5844730A JPS5844730A (ja) | 1983-03-15 |
JPS6243338B2 true JPS6243338B2 (ja) | 1987-09-12 |
Family
ID=15317448
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56142528A Granted JPS5844730A (ja) | 1981-09-11 | 1981-09-11 | 半導体装置の電極・配線 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5844730A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02297519A (ja) * | 1989-05-12 | 1990-12-10 | Matsushita Electric Ind Co Ltd | 液晶表示装置の駆動方法 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0878410A (ja) * | 1994-09-05 | 1996-03-22 | Mitsubishi Electric Corp | 配線接続部及びその製造方法 |
JP6209040B2 (ja) * | 2013-09-30 | 2017-10-04 | 東芝ホクト電子株式会社 | サーマルヘッド |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5119968A (ja) * | 1974-08-12 | 1976-02-17 | Hitachi Ltd | |
JPS55156365A (en) * | 1979-05-24 | 1980-12-05 | Toshiba Corp | Semiconductor device |
-
1981
- 1981-09-11 JP JP56142528A patent/JPS5844730A/ja active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5119968A (ja) * | 1974-08-12 | 1976-02-17 | Hitachi Ltd | |
JPS55156365A (en) * | 1979-05-24 | 1980-12-05 | Toshiba Corp | Semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02297519A (ja) * | 1989-05-12 | 1990-12-10 | Matsushita Electric Ind Co Ltd | 液晶表示装置の駆動方法 |
Also Published As
Publication number | Publication date |
---|---|
JPS5844730A (ja) | 1983-03-15 |
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