JPS6240865B2 - - Google Patents

Info

Publication number
JPS6240865B2
JPS6240865B2 JP57097312A JP9731282A JPS6240865B2 JP S6240865 B2 JPS6240865 B2 JP S6240865B2 JP 57097312 A JP57097312 A JP 57097312A JP 9731282 A JP9731282 A JP 9731282A JP S6240865 B2 JPS6240865 B2 JP S6240865B2
Authority
JP
Japan
Prior art keywords
film
gate electrode
polycrystalline silicon
channel mos
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57097312A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58215064A (ja
Inventor
Yoshihisa Mizutani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP57097312A priority Critical patent/JPS58215064A/ja
Publication of JPS58215064A publication Critical patent/JPS58215064A/ja
Publication of JPS6240865B2 publication Critical patent/JPS6240865B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00Three-dimensional [3D] integrated devices

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
JP57097312A 1982-06-07 1982-06-07 積層型半導体装置 Granted JPS58215064A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57097312A JPS58215064A (ja) 1982-06-07 1982-06-07 積層型半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57097312A JPS58215064A (ja) 1982-06-07 1982-06-07 積層型半導体装置

Publications (2)

Publication Number Publication Date
JPS58215064A JPS58215064A (ja) 1983-12-14
JPS6240865B2 true JPS6240865B2 (enrdf_load_stackoverflow) 1987-08-31

Family

ID=14188963

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57097312A Granted JPS58215064A (ja) 1982-06-07 1982-06-07 積層型半導体装置

Country Status (1)

Country Link
JP (1) JPS58215064A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6045053A (ja) * 1983-08-22 1985-03-11 Mitsubishi Electric Corp 半導体装置

Also Published As

Publication number Publication date
JPS58215064A (ja) 1983-12-14

Similar Documents

Publication Publication Date Title
US7981738B2 (en) Semiconductor memory device and a method of manufacturing the same
KR100253032B1 (ko) 스테이틱 랜덤 액세스 메모리를 갖는 반도체 메모리 장치 및 그의 제조방법
JP3167366B2 (ja) 集積回路装置およびその製造方法
JPH05167041A (ja) ポリシリコントランジスタ負荷を有する積層型cmos sram
US6300229B1 (en) Semiconductor device and method of manufacturing the same
JPS6146980B2 (enrdf_load_stackoverflow)
JPS6218064A (ja) スタテイツク・ライト・リ−ド・メモリにおける交差結合の製作方法
JPH0770624B2 (ja) 半導体集積回路
US5497022A (en) Semiconductor device and a method of manufacturing thereof
US6525382B1 (en) Semiconductor memory device and method of manufacturing the same
JP3712313B2 (ja) Sramセルの構造及びその製造方法
JP2950232B2 (ja) 半導体記憶装置の製造方法
JP3436462B2 (ja) 半導体装置
KR0155182B1 (ko) Tft 부하를 갖는 반도체 스태틱 메모리 장치
US20020027227A1 (en) Semiconductor memory device having a trench and a gate electrode vertically formed on a wall of the trench
JPS6240864B2 (enrdf_load_stackoverflow)
JPS6240865B2 (enrdf_load_stackoverflow)
JP2550119B2 (ja) 半導体記憶装置
JP2877069B2 (ja) スタティック型半導体メモリ装置
JPH0992731A (ja) Lddトランジスタを有する半導体装置
JP2621824B2 (ja) 半導体装置の製造方法
US6713345B1 (en) Semiconductor memory device having a trench and a gate electrode vertically formed on a wall of the trench
KR960015786B1 (ko) 반도체장치 및 그의 제조방법
KR100287164B1 (ko) 반도체장치 및 그 제조방법
JPH04233755A (ja) スタティックランダムアクセス・メモリセルとスタティックランダムアクセスmosfetメモリセル