JPS6238863B2 - - Google Patents

Info

Publication number
JPS6238863B2
JPS6238863B2 JP53131639A JP13163978A JPS6238863B2 JP S6238863 B2 JPS6238863 B2 JP S6238863B2 JP 53131639 A JP53131639 A JP 53131639A JP 13163978 A JP13163978 A JP 13163978A JP S6238863 B2 JPS6238863 B2 JP S6238863B2
Authority
JP
Japan
Prior art keywords
frame
lead
outer frame
tie bar
effective
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53131639A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5559749A (en
Inventor
Kazuo Shimizu
Kazuo Hoya
Fumihito Inoe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13163978A priority Critical patent/JPS5559749A/ja
Publication of JPS5559749A publication Critical patent/JPS5559749A/ja
Publication of JPS6238863B2 publication Critical patent/JPS6238863B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP13163978A 1978-10-27 1978-10-27 Lead frame Granted JPS5559749A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13163978A JPS5559749A (en) 1978-10-27 1978-10-27 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13163978A JPS5559749A (en) 1978-10-27 1978-10-27 Lead frame

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP6392887A Division JPS62252959A (ja) 1987-03-20 1987-03-20 リ−ドフレ−ム

Publications (2)

Publication Number Publication Date
JPS5559749A JPS5559749A (en) 1980-05-06
JPS6238863B2 true JPS6238863B2 (fr) 1987-08-20

Family

ID=15062750

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13163978A Granted JPS5559749A (en) 1978-10-27 1978-10-27 Lead frame

Country Status (1)

Country Link
JP (1) JPS5559749A (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02105867U (fr) * 1989-02-10 1990-08-22

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5749129A (en) * 1980-09-09 1982-03-20 Matsushita Electric Ind Co Ltd Method of producing electronic part
JPS5827332A (ja) * 1981-08-11 1983-02-18 Toshiba Corp リードフレームを用いた半導体装置の製造方法
JPS58154240A (ja) * 1982-03-10 1983-09-13 Hitachi Ltd 樹脂封止形半導体装置
JPS58170834U (ja) * 1982-05-07 1983-11-15 日本電気株式会社 リ−ドフレ−ムのアイランド吊り構造
JPS6155349U (fr) * 1984-08-29 1986-04-14
JPS62190858A (ja) * 1986-02-18 1987-08-21 Mitsubishi Electric Corp 半導体装置
JPS63147832U (fr) * 1987-03-19 1988-09-29
JPS62252959A (ja) * 1987-03-20 1987-11-04 Hitachi Ltd リ−ドフレ−ム
JP2803642B2 (ja) * 1996-06-27 1998-09-24 日本電気株式会社 半導体装置
CN107845575A (zh) * 2017-11-03 2018-03-27 浙江人和光伏科技有限公司 一种薄片二极管的生产方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5363979A (en) * 1976-11-19 1978-06-07 Hitachi Ltd Sealing method of semiconductor element and lead frame used for the same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5363979A (en) * 1976-11-19 1978-06-07 Hitachi Ltd Sealing method of semiconductor element and lead frame used for the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02105867U (fr) * 1989-02-10 1990-08-22

Also Published As

Publication number Publication date
JPS5559749A (en) 1980-05-06

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