JPS6235144B2 - - Google Patents

Info

Publication number
JPS6235144B2
JPS6235144B2 JP54075156A JP7515679A JPS6235144B2 JP S6235144 B2 JPS6235144 B2 JP S6235144B2 JP 54075156 A JP54075156 A JP 54075156A JP 7515679 A JP7515679 A JP 7515679A JP S6235144 B2 JPS6235144 B2 JP S6235144B2
Authority
JP
Japan
Prior art keywords
data
bus
memory
buffer
corrected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54075156A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5525194A (en
Inventor
Ii Suurufuroo Robaato
Emu Dorobunii Edowaado
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HANEIUERU INFUOOMEISHON SHISUTEMUSU Inc
Original Assignee
HANEIUERU INFUOOMEISHON SHISUTEMUSU Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HANEIUERU INFUOOMEISHON SHISUTEMUSU Inc filed Critical HANEIUERU INFUOOMEISHON SHISUTEMUSU Inc
Publication of JPS5525194A publication Critical patent/JPS5525194A/ja
Publication of JPS6235144B2 publication Critical patent/JPS6235144B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)
  • Debugging And Monitoring (AREA)
  • Bus Control (AREA)
  • Hardware Redundancy (AREA)
JP7515679A 1978-08-04 1979-06-14 Bus device Granted JPS5525194A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/930,966 US4225959A (en) 1978-08-04 1978-08-04 Tri-state bussing system

Publications (2)

Publication Number Publication Date
JPS5525194A JPS5525194A (en) 1980-02-22
JPS6235144B2 true JPS6235144B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1987-07-30

Family

ID=25460029

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7515679A Granted JPS5525194A (en) 1978-08-04 1979-06-14 Bus device

Country Status (6)

Country Link
US (1) US4225959A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS5525194A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
AU (1) AU520932B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CA (1) CA1149068A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE2915113A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
FR (1) FR2432736A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4336611A (en) * 1979-12-03 1982-06-22 Honeywell Information Systems Inc. Error correction apparatus and method
FR2528613B1 (fr) * 1982-06-09 1991-09-20 Hitachi Ltd Memoire a semi-conducteurs
US4663728A (en) * 1984-06-20 1987-05-05 Weatherford James R Read/modify/write circuit for computer memory operation
US4962474A (en) * 1987-11-17 1990-10-09 International Business Machines Corporation LSSD edge detection logic for asynchronous data interface
US5373514A (en) * 1990-09-20 1994-12-13 Synopsys, Inc. Three-state bus structure and method for generating test vectors while avoiding contention and/or floating outputs on the three-state bus
JPH04162300A (ja) * 1990-10-26 1992-06-05 Nec Corp 半導体メモリ
JP2020198044A (ja) * 2019-06-05 2020-12-10 富士通株式会社 並列処理装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3573728A (en) * 1969-01-09 1971-04-06 Ibm Memory with error correction for partial store operation
US3693153A (en) * 1971-07-09 1972-09-19 Bell Telephone Labor Inc Parity check apparatus and method for minicomputers
US3809884A (en) * 1972-11-15 1974-05-07 Honeywell Inf Systems Apparatus and method for a variable memory cycle in a data processing unit
US4037091A (en) * 1976-04-05 1977-07-19 Bell Telephone Laboratories, Incorporated Error correction circuit utilizing multiple parity bits
US4058851A (en) * 1976-10-18 1977-11-15 Sperry Rand Corporation Conditional bypass of error correction for dual memory access time selection

Also Published As

Publication number Publication date
CA1149068A (en) 1983-06-28
AU4911779A (en) 1980-02-07
DE2915113C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1989-01-05
AU520932B2 (en) 1982-03-04
US4225959A (en) 1980-09-30
DE2915113A1 (de) 1980-02-14
FR2432736B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1983-07-29
FR2432736A1 (fr) 1980-02-29
JPS5525194A (en) 1980-02-22

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