JPS6232827B2 - - Google Patents

Info

Publication number
JPS6232827B2
JPS6232827B2 JP56091922A JP9192281A JPS6232827B2 JP S6232827 B2 JPS6232827 B2 JP S6232827B2 JP 56091922 A JP56091922 A JP 56091922A JP 9192281 A JP9192281 A JP 9192281A JP S6232827 B2 JPS6232827 B2 JP S6232827B2
Authority
JP
Japan
Prior art keywords
memory
address
test
data
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56091922A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57205900A (en
Inventor
Tatsuo Sato
Takashi Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56091922A priority Critical patent/JPS57205900A/ja
Publication of JPS57205900A publication Critical patent/JPS57205900A/ja
Publication of JPS6232827B2 publication Critical patent/JPS6232827B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
JP56091922A 1981-06-15 1981-06-15 Testing method of memory Granted JPS57205900A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56091922A JPS57205900A (en) 1981-06-15 1981-06-15 Testing method of memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56091922A JPS57205900A (en) 1981-06-15 1981-06-15 Testing method of memory

Publications (2)

Publication Number Publication Date
JPS57205900A JPS57205900A (en) 1982-12-17
JPS6232827B2 true JPS6232827B2 (OSRAM) 1987-07-16

Family

ID=14040069

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56091922A Granted JPS57205900A (en) 1981-06-15 1981-06-15 Testing method of memory

Country Status (1)

Country Link
JP (1) JPS57205900A (OSRAM)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59124097A (ja) * 1982-12-28 1984-07-18 Toshiba Corp メモリ検定方法
JPS6219951A (ja) * 1985-07-17 1987-01-28 Fujitsu Ltd 半導体デイスク装置
JPS647240A (en) * 1987-06-30 1989-01-11 Hioki Electric Works Memory capacity discriminating method for memory card
GB2439968B (en) * 2006-07-07 2011-05-25 Advanced Risc Mach Ltd Memory testing
JP6071930B2 (ja) * 2014-03-14 2017-02-01 株式会社東芝 半導体集積回路

Also Published As

Publication number Publication date
JPS57205900A (en) 1982-12-17

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