JPS6230657B2 - - Google Patents

Info

Publication number
JPS6230657B2
JPS6230657B2 JP57138494A JP13849482A JPS6230657B2 JP S6230657 B2 JPS6230657 B2 JP S6230657B2 JP 57138494 A JP57138494 A JP 57138494A JP 13849482 A JP13849482 A JP 13849482A JP S6230657 B2 JPS6230657 B2 JP S6230657B2
Authority
JP
Japan
Prior art keywords
transmission
controller
subloop
bus
conversion module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57138494A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5930150A (ja
Inventor
Eiji Tooyama
Shinya Kikuchi
Akira Sugano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Industry and Control Solutions Co Ltd
Original Assignee
Hitachi Engineering Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Engineering Co Ltd, Hitachi Ltd filed Critical Hitachi Engineering Co Ltd
Priority to JP57138494A priority Critical patent/JPS5930150A/ja
Publication of JPS5930150A publication Critical patent/JPS5930150A/ja
Publication of JPS6230657B2 publication Critical patent/JPS6230657B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/20Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
JP57138494A 1982-08-11 1982-08-11 分散形階層システムのn:1バツクアツプ方式 Granted JPS5930150A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57138494A JPS5930150A (ja) 1982-08-11 1982-08-11 分散形階層システムのn:1バツクアツプ方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57138494A JPS5930150A (ja) 1982-08-11 1982-08-11 分散形階層システムのn:1バツクアツプ方式

Publications (2)

Publication Number Publication Date
JPS5930150A JPS5930150A (ja) 1984-02-17
JPS6230657B2 true JPS6230657B2 (enrdf_load_stackoverflow) 1987-07-03

Family

ID=15223419

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57138494A Granted JPS5930150A (ja) 1982-08-11 1982-08-11 分散形階層システムのn:1バツクアツプ方式

Country Status (1)

Country Link
JP (1) JPS5930150A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPS5930150A (ja) 1984-02-17

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