JPS62293343A - ブ−ス変換回路 - Google Patents
ブ−ス変換回路Info
- Publication number
- JPS62293343A JPS62293343A JP61135162A JP13516286A JPS62293343A JP S62293343 A JPS62293343 A JP S62293343A JP 61135162 A JP61135162 A JP 61135162A JP 13516286 A JP13516286 A JP 13516286A JP S62293343 A JPS62293343 A JP S62293343A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- level
- transistor
- output
- supplied
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/40—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using contact-making devices, e.g. electromagnetic relay
- G06F7/44—Multiplying; Dividing
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
- G06F7/5332—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by skipping over strings of zeroes or ones, e.g. using the Booth Algorithm
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Mathematical Analysis (AREA)
- Computational Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Electromagnetism (AREA)
- Logic Circuits (AREA)
- Document Processing Apparatus (AREA)
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61135162A JPS62293343A (ja) | 1986-06-11 | 1986-06-11 | ブ−ス変換回路 |
| EP87106863A EP0249040B1 (en) | 1986-06-11 | 1987-05-12 | Booth's conversion circuit |
| DE87106863T DE3786607T2 (de) | 1986-06-11 | 1987-05-12 | Booth-wandlerschaltung. |
| US07/049,141 US4798980A (en) | 1986-06-11 | 1987-05-13 | Booth's conversion circuit |
| KR1019870005901A KR900003565B1 (ko) | 1986-06-11 | 1987-06-11 | 부스(booth) 변환회로 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61135162A JPS62293343A (ja) | 1986-06-11 | 1986-06-11 | ブ−ス変換回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62293343A true JPS62293343A (ja) | 1987-12-19 |
| JPH0448254B2 JPH0448254B2 (enExample) | 1992-08-06 |
Family
ID=15145272
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61135162A Granted JPS62293343A (ja) | 1986-06-11 | 1986-06-11 | ブ−ス変換回路 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4798980A (enExample) |
| EP (1) | EP0249040B1 (enExample) |
| JP (1) | JPS62293343A (enExample) |
| KR (1) | KR900003565B1 (enExample) |
| DE (1) | DE3786607T2 (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04227534A (ja) * | 1990-03-16 | 1992-08-17 | C Cube Microsyst | アレイ乗算器 |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5041742A (en) * | 1990-05-09 | 1991-08-20 | Motorola, Inc. | Structured scan path circuit for incorporating domino logic |
| EP0589148A1 (en) * | 1992-09-22 | 1994-03-30 | Motorola, Inc. | Multiplexer circuit for modified booth's multiplier or the like |
| US5508641A (en) * | 1994-12-20 | 1996-04-16 | International Business Machines Corporation | Integrated circuit chip and pass gate logic family therefor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59202542A (ja) * | 1983-05-02 | 1984-11-16 | Matsushita Electric Ind Co Ltd | デコ−ダ回路 |
| JPS6055439A (ja) * | 1983-09-05 | 1985-03-30 | Matsushita Electric Ind Co Ltd | テコ−ダ回路 |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4238833A (en) * | 1979-03-28 | 1980-12-09 | Monolithic Memories, Inc. | High-speed digital bus-organized multiplier/divider system |
| US4566064A (en) * | 1982-05-10 | 1986-01-21 | American Microsystems, Inc. | Combinational logic structure using PASS transistors |
| US4570085A (en) * | 1983-01-17 | 1986-02-11 | Commodore Business Machines Inc. | Self booting logical AND circuit |
| US4595845A (en) * | 1984-03-13 | 1986-06-17 | Mostek Corporation | Non-overlapping clock CMOS circuit with two threshold voltages |
| JPS6182527A (ja) * | 1984-09-29 | 1986-04-26 | Mitsubishi Electric Corp | パルス発生回路 |
| US4716312A (en) * | 1985-05-07 | 1987-12-29 | California Institute Of Technology | CMOS logic circuit |
| JPH105732A (ja) * | 1996-06-26 | 1998-01-13 | Yanmar Agricult Equip Co Ltd | 生ゴミ処理装置 |
-
1986
- 1986-06-11 JP JP61135162A patent/JPS62293343A/ja active Granted
-
1987
- 1987-05-12 DE DE87106863T patent/DE3786607T2/de not_active Expired - Fee Related
- 1987-05-12 EP EP87106863A patent/EP0249040B1/en not_active Expired - Lifetime
- 1987-05-13 US US07/049,141 patent/US4798980A/en not_active Expired - Lifetime
- 1987-06-11 KR KR1019870005901A patent/KR900003565B1/ko not_active Expired
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59202542A (ja) * | 1983-05-02 | 1984-11-16 | Matsushita Electric Ind Co Ltd | デコ−ダ回路 |
| JPS6055439A (ja) * | 1983-09-05 | 1985-03-30 | Matsushita Electric Ind Co Ltd | テコ−ダ回路 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04227534A (ja) * | 1990-03-16 | 1992-08-17 | C Cube Microsyst | アレイ乗算器 |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0249040A2 (en) | 1987-12-16 |
| EP0249040A3 (en) | 1990-09-19 |
| JPH0448254B2 (enExample) | 1992-08-06 |
| DE3786607D1 (de) | 1993-08-26 |
| US4798980A (en) | 1989-01-17 |
| EP0249040B1 (en) | 1993-07-21 |
| DE3786607T2 (de) | 1993-11-04 |
| KR880000857A (ko) | 1988-03-30 |
| KR900003565B1 (ko) | 1990-05-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |