JPS62281436A - Electronic device - Google Patents
Electronic deviceInfo
- Publication number
- JPS62281436A JPS62281436A JP61123400A JP12340086A JPS62281436A JP S62281436 A JPS62281436 A JP S62281436A JP 61123400 A JP61123400 A JP 61123400A JP 12340086 A JP12340086 A JP 12340086A JP S62281436 A JPS62281436 A JP S62281436A
- Authority
- JP
- Japan
- Prior art keywords
- pellet
- leads
- conductors
- junction
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims abstract description 37
- 239000008188 pellet Substances 0.000 claims abstract description 30
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 claims abstract 2
- 239000011521 glass Substances 0.000 claims description 8
- 239000000956 alloy Substances 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 abstract description 6
- 239000000919 ceramic Substances 0.000 abstract description 2
- 210000004907 gland Anatomy 0.000 abstract 2
- 229910001252 Pd alloy Inorganic materials 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 239000011800 void material Substances 0.000 abstract 1
- 238000007789 sealing Methods 0.000 description 12
- 230000000694 effects Effects 0.000 description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 239000005394 sealing glass Substances 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
〔産業上の利用分野〕
本発明は、電子装置、特に、その配線技術の改良に関し
、例えば、セラミックを用いたフラット・バフケージ（
Ｆ Ｐ Ｇ）を有する半導体装Ｗｔ（以下、ＦＰＧＩＣ
という、）に利用して有効な技術に関する。Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an electronic device, and in particular to an improvement in wiring technology thereof.
FPG) semiconductor device Wt (hereinafter referred to as FPGIC)
Regarding effective technology that can be used for
ＩＣの使用分野の拡大に伴って、そのパッケージ並びに
リード（ピン）配置が多様化している。As the fields of use of ICs expand, their packages and lead (pin) arrangements are diversifying.
そして、ＦＰＧＩＣにおいてパッケージまたはリード配
置を変更する場合、ペレットにおける集積回路のレイア
ウトをこれに対応するように設計変更することが、一般
的に考えられる。When changing the package or lead arrangement in an FPGIC, it is generally considered to change the design of the integrated circuit layout in the pellet to correspond to the change.
なお、ＩＣパッケージの多様化技術を述べである例とし
ては、日経マグロウヒル社発行「別冊マイクロデバイセ
ズＮ１２Ｊ１９８４年６月１１日発行Ｐ１３０〜Ｐ１６
８、がある。An example of the diversification technology of IC packages is "Bessatsu Micro Devices N12J, June 11, 1984, published by Nikkei McGraw-Hill, pp. 130-16.
There is 8.
しかし、ＦＰＧ［Ｃにおいて、例えば、電源用リードお
よびグランド用リードの配置の指定が変更されただけの
場合でも、集積回路のレイアウトを当該リード配置に合
うように変更していたのでは、開発に多大の手間および
費用がかかるという問題点があることが、本発明者によ
って明らかにされた。However, in FPG[C, for example, even if the designation of the placement of power supply leads and ground leads is only changed, it would be difficult to develop the integrated circuit layout by changing it to match the lead placement. The inventor of the present invention has found that there is a problem in that it requires a great deal of effort and expense.
本発明の目的は、レイアウトの変更の必要性を抑制する
ことができる電子装置技術を提供することにある。An object of the present invention is to provide electronic device technology that can suppress the necessity of changing the layout.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
ｃ問題点を解決するための手段〕
本願において開示される発明のうち代表的なものの概要
を説明すれば、次の通りである。Measures for Solving Problems c] Representative inventions disclosed in this application will be summarized as follows.
すなわち、ペレットの外方に中継用導体を配設するとと
もに、この導体にはペレットにおける回路の一部とリー
ドの一部とをそれぞれ接続したものである。That is, a relay conductor is disposed outside the pellet, and a part of the circuit and a part of the lead in the pellet are respectively connected to this conductor.
前記した手段によれば、例えば、電源用リードやグラン
ド用リード等の配置が変更された場合等のように簡単な
変更の場合、ペレットにおけるレイアウトを変更しなく
とも、ベレット上の電源用またはグランド用パッドと電
源用またはグランド用リードとを中継用導体を介してそ
れぞれ電気的に接続させることができるため、リード配
置変更に伴う集積回路についての設計変更の必要性を抑
制することができる。According to the above-mentioned means, in the case of a simple change such as when the arrangement of power supply leads, ground leads, etc. is changed, the power supply or ground leads on the pellet can be changed without changing the layout on the pellet. Since the power pad and the power supply or ground lead can be electrically connected to each other via the relay conductor, it is possible to suppress the need for a design change of the integrated circuit due to a change in the lead arrangement.
第１図は本発明の一実施例であるＦＰＧＩＣを示すキヤ
ツジを除いた伏態の平面図、第２図は第１図のｎ−ｕ線
断面に相当する縦断面図、第３図は作用を説明するため
の平面図である。Fig. 1 is a plan view of an FPGIC according to an embodiment of the present invention in a lying position with the cage removed; Fig. 2 is a vertical sectional view corresponding to the nu line cross section of Fig. 1; FIG.
本実施例において、このＦＰＧＩＣはセラミックからな
るベースｌを備えており、ベースｌにはキャビティ２が
その上面における略中央部に配されて没設されている。In this embodiment, this FPGIC includes a base 1 made of ceramic, and a cavity 2 is sunk in the base 1, and is disposed approximately in the center of the upper surface of the base 1.
キャビティ２の底面上にはマウント部３が形成されてお
り、マウント部３にはペレット４がボンディングされて
いる。ペレット４には集積回路（図示せず）が形成され
ており、ペレット４の上面における周辺部には集積回路
に接続されている電極パッド５が複数、互いに対向する
一対の端辺に配列されて形成されている。A mount portion 3 is formed on the bottom surface of the cavity 2, and a pellet 4 is bonded to the mount portion 3. An integrated circuit (not shown) is formed on the pellet 4, and a plurality of electrode pads 5 connected to the integrated circuit are arranged on a pair of opposing edges on the periphery of the upper surface of the pellet 4. It is formed.
ベース１の上面にはリードフレーム（図示せず）から形
成されたインナリード６が複数、電極パッド５に対向す
る一対の端辺に配されてメタライズ部を介した接着また
は溶着等の適当な手段により固着されており、各インナ
リード６にはアウタリード７が一体的に連設されている
。各インナリード６とペレット４における所定の電極パ
ッド５との間にはボンディングワイヤ８がそれぞれ橋絡
されており、これによって電極パッド５とインナリード
６とは電気的に接続されるため、ペレット４の集積回路
はアウタリード７に導出されることになる。A plurality of inner leads 6 formed from a lead frame (not shown) are arranged on the upper surface of the base 1 at a pair of end sides facing the electrode pads 5, and are bonded or welded by appropriate means via metallized parts. An outer lead 7 is integrally connected to each inner lead 6. A bonding wire 8 is bridged between each inner lead 6 and a predetermined electrode pad 5 on the pellet 4, and as a result, the electrode pad 5 and the inner lead 6 are electrically connected. The integrated circuit will be led out to the outer lead 7.
ベース１の上面には第１および第２中継用導体９および
１０が、インナリード６が配設されていない両脇の端辺
の空所であって、後記するように封着部となる部分にそ
れぞれ配されて、ＩＮ（Ａｇ）−パラジウム（Ｐｄ）基
合金を用いてスクリーン印刷のような厚膜形成技術等の
適当な手段により形成されている。これら導体９．１０
はインナリード６が配された片側の端辺から他側の端辺
にかけてそれぞれ延設されている。The first and second relay conductors 9 and 10 are placed on the upper surface of the base 1 in the empty space on both sides where the inner lead 6 is not provided, and as will be described later, the part that will become a sealing part. They are formed by appropriate means such as thick film forming technology such as screen printing using an IN(Ag)-palladium (Pd) based alloy. These conductors9.10
extend from one end where the inner lead 6 is arranged to the other end.
第１中継用導体９０両端部にはポンディングパッド９ａ
、９ｂがそれぞれ形成されており、一方のポンディング
パッド９ａと、ペレット４の電極パッド５のうち電源用
パッド５ａとの間にはボンディングワイヤ８ａが橋絡さ
れており、他方のポンディングパッド９ｂと、インナリ
ード６のうち電源用アウタリード７ｂに接続されたイン
ナリード６ｂとの間にはボンディングワイヤ８ｂがそれ
ぞれ橋象各されている。これにより、ペレット４の電源
回路（図示せず）は電源用アウタリード７ｂに第１中継
用導体９およびインナリード６ｂを介してそれぞれ電気
的に接続されている。Bonding pads 9a are provided at both ends of the first relay conductor 90.
, 9b are formed, and a bonding wire 8a is bridged between one of the bonding pads 9a and the power supply pad 5a of the electrode pads 5 of the pellet 4, and the other bonding pad 9b A bonding wire 8b is bridged between the inner lead 6b of the inner lead 6 and the inner lead 6b connected to the power supply outer lead 7b. Thereby, the power supply circuit (not shown) of the pellet 4 is electrically connected to the power supply outer lead 7b via the first relay conductor 9 and the inner lead 6b.
一方、第２中継用導体１０の両端部にはポンディングパ
ッド１０ｃ、１０ｄがそれぞれ形成されており、一方の
ポンディングパッド１０ｃと、ペレット４の電極パッド
５のうちグランド用電掻パッド５ｃとの間にはボンディ
ングワイヤ８ｃが橋絡されており、他方のポンディング
パッド１０ｄと、インナリード７のうちグランド用アウ
タリード７ｄに接続されたインナリード６ｄとの間には
、ボンディングワイヤ８ｄがそれぞれ橋絡されている、
これにより、ペレット４のグランド回路（図示せず）は
グランド用アウタリード７ｄに第２中継用導体１０およ
びインナリード６ｄを介してそれぞれ電気的に接続され
ている。On the other hand, bonding pads 10c and 10d are formed at both ends of the second relay conductor 10, and one of the bonding pads 10c is connected to the grounding pad 5c of the electrode pads 5 of the pellet 4. A bonding wire 8c is bridged between them, and a bonding wire 8d is bridged between the other bonding pad 10d and an inner lead 6d of the inner lead 7 connected to the grounding outer lead 7d. has been,
Thereby, the ground circuit (not shown) of the pellet 4 is electrically connected to the grounding outer lead 7d via the second relay conductor 10 and the inner lead 6d.
ベース１の上面におけるキャビティ４の開口周縁部には
低融点ガラスからなる封着部１１が形成されており、こ
の封着部１１によってキャンプ１２がベース１に接合さ
れることにより、気密封止パッケージ１３が形成されて
キャビティ４の内部が気密封止されている。A sealing part 11 made of low-melting glass is formed around the opening of the cavity 4 on the upper surface of the base 1, and the camp 12 is joined to the base 1 by this sealing part 11, thereby forming an airtightly sealed package. 13 is formed, and the inside of the cavity 4 is hermetically sealed.
ここで、封着部１１は、ベース１上面およびキャップ１
２下面の外周縁部に低融点ガラスをスクリーン印刷等に
よって塗布された後、互いに接合された状態で封止炉を
通されて溶着されることにより形成される。このとき、
前記中継用導体９．１０は封着部１１内に封止込まれる
ことになるが、Ａｇ−Ｐｄ基合金等の適当な材料を使用
することにより、導体のガラス材料内への拡散は防止す
ることができる。Here, the sealing part 11 includes the upper surface of the base 1 and the cap 1.
After applying low-melting point glass to the outer peripheral edge of the lower surface of 2 by screen printing or the like, the two are bonded together and passed through a sealing furnace to be welded. At this time,
The relay conductors 9 and 10 will be sealed within the sealing part 11, but diffusion of the conductors into the glass material can be prevented by using a suitable material such as an Ag-Pd based alloy. be able to.
他方、中継用導体を封着部１１内に配設することにより
、パッケージ１３の外形寸法の拡大化が回避されること
になる。また、ワイヤボンディング以前に中継用導体９
．１０上に封着ガラスを塗布する場合には、ワイヤをボ
ンディングするためのパッド部をそれぞれ開設しておけ
ば、これら導体９．１０に前記各ワイヤ８ａ〜８ｄをボ
ンディングすることができる。さらに、これらワイヤの
一部は封着部１１で押さえつけられるが、ガラスは熔融
すると、きわめて粘度が低下するため、断線等の損傷は
発生しない。On the other hand, by arranging the relay conductor within the sealing portion 11, an increase in the external dimensions of the package 13 can be avoided. Also, before wire bonding, the relay conductor 9
．． When sealing glass is applied on the conductors 9 and 10, each of the wires 8a to 8d can be bonded to the conductors 9 and 10 by providing pad portions for bonding the wires. Furthermore, although some of these wires are pressed down by the sealing part 11, the viscosity of the glass is extremely reduced when it is melted, so no damage such as wire breakage occurs.
次に作用を説明する。Next, the effect will be explained.
システム（ユーザ）からの要求等によって、電源用アウ
タリードとグランド用アウタリードとの関係位置が変更
される場合における本実施例の変更対策を、電源用アウ
タリード７ｂおよびグランド用アウタリード７ｄの位置
が、第１図に示されている位置から第３ＦＩ！Ｊに示さ
れている位置に変更された場合を例にして説明する。In the case where the relative position between the power supply outer lead and the grounding outer lead is changed due to a request from the system (user), etc., the change countermeasure of this embodiment is such that the position of the power supply outer lead 7b and the grounding outer lead 7d is 3rd FI from the position shown in the figure! The case where the position is changed to the position shown in J will be explained as an example.
第３図に示されているように、位置変更された電源用ア
ウタリード７ｂ″に接続されたインナリード６ｂ’ と
電源用パッド５ａとの間には、ボンディングワイヤ３ａ
’ が橋絡される。他方、グランド用アウタリード７ｄ
’ に接続されたインナリード６ｄ’ とグランド用パ
ッド５Ｃとの間には、ボンディングワイヤ３ｃ’ がそ
れぞれＪｌｉ＆各される。As shown in FIG. 3, a bonding wire 3a is connected between the inner lead 6b' connected to the power supply outer lead 7b" whose position has been changed and the power supply pad 5a.
' is bridged. On the other hand, the outer lead for ground 7d
A bonding wire 3c' is connected between the inner lead 6d' connected to the ground pad 5C and the grounding pad 5C, respectively.
この場合、両中継用導体９．１０は使用されない。In this case, both relay conductors 9,10 are not used.
そして、電源用パッド５ａがボンディングワイヤ８ａ’
により橋絡されているため、位置変更された電源用ア
ウタリード７ｂ’ はベレット４における電源回路に、
インナリード６ｂ’ およびボンディングワイヤ８ａ’
を介してそれぞれ電気的に接続されることになる。ま
た、グランド用パッド５Ｃがボンディングワイヤ８ｃ’
により１喬本各されているため、位置変更されたグ
ランド用アウタリード７ｄ’ はペレット４におけるグ
ランド回路にインナリード５ｄ’ およびボンディング
ワイヤ８Ｃ°を介してそれぞれ電気的に接続されること
になる。つまり、電源用およびグランド用アウタリード
７ｂ’ 、７ｄ’ の位置が変更された場合であっても
、電源用およびグランド用パッド５ａ、５Ｃの位置、す
なわち、ペレットの集積回路についてのレイアウトは変
更しなくても済む。Then, the power supply pad 5a is connected to the bonding wire 8a'
Since the outer lead 7b' for the power supply whose position has been changed is bridged by the power supply circuit in the bellet 4,
Inner lead 6b' and bonding wire 8a'
They will be electrically connected to each other via. In addition, the ground pad 5C is connected to the bonding wire 8c'
Since the grounding outer lead 7d' whose position has been changed is electrically connected to the grounding circuit in the pellet 4 via the inner lead 5d' and the bonding wire 8C. In other words, even if the positions of the power and ground outer leads 7b' and 7d' are changed, the positions of the power and ground pads 5a and 5C, that is, the layout of the pellet integrated circuit, remain unchanged. I can get away with it.
前記実施例によれば次の効果が得られる。According to the embodiment described above, the following effects can be obtained.
＋１１ ペレットの外方に一対の中継用導体を配設す
ることにより、電源用およびグランド用リードの配置が
変更された場合、ペレットにおけるレイアウトを変更し
なくとも、ベレット上の電源用およびレイアウト用パッ
ドと、電源用およびグランド用リードとを中継用導体を
介して電気的に接続することができるため、ペレットに
おける集積回路のレイアウトを変更する必要がなく、半
導体装置の開発についての手間、費用等を軽減化するこ
とができる。+11 If the arrangement of the power and ground leads is changed by placing a pair of relay conductors on the outside of the pellet, the power and layout pads on the pellet can be changed without changing the layout on the pellet. , power supply and ground leads can be electrically connected via a relay conductor, so there is no need to change the layout of the integrated circuit in the pellet, reducing the time and cost involved in developing semiconductor devices. It can be reduced.
（２）中継用導体をガラス封着部となる部分に配設する
ことにより、パンケージの大型化を抑制することができ
るため、実装の高密度化の妨げを防止することができる
。(2) By arranging the relay conductor in the portion that will become the glass sealing part, it is possible to suppress the increase in size of the pan cage, and therefore it is possible to prevent interference with higher packaging density.
（３）中継用導体をＡｇ−Ｐｄ基合金を用いて形成する
ことにより、封着ガラスへの拡散を防止することができ
るため、ＩＣの品質および信頼性の低下を防止すること
ができる。(3) By forming the relay conductor using an Ag-Pd-based alloy, it is possible to prevent diffusion into the sealing glass, thereby preventing deterioration in the quality and reliability of the IC.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で覆々変更可能
であることはいうまでもない。Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the Examples described above, and it is possible to make various changes without departing from the gist thereof. Not even.
例えば、中継用導体は電源用およびグランド用の位置変
更に使用するに限らず、信号回路のレイアウト変更に使
用してもよい。For example, the relay conductor is not limited to being used to change the position of power supply and ground, but may also be used to change the layout of a signal circuit.
また、中継用導体は両端のある直線形状に形成するに限
らず、環状に形成してもよい。Furthermore, the relay conductor is not limited to being formed in a linear shape with both ends, but may be formed in an annular shape.
中継用導体はガラス封着部に配設するに限らず、封着部
よりも内側に配設してもよい。The relay conductor is not limited to being disposed in the glass sealing part, but may be disposed inside the sealing part.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野であるＦＰＧＩＣに通用し
た場合について説明したが、それに限定されるものでは
なく、半時別注文の半導体装置等にも適用することがで
きる。In the above explanation, the invention made by the present inventor was mainly applied to FPGIC, which is the background application field, but it is not limited to this, and can also be applied to semiconductor devices that are ordered by the hour. Can be applied.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、次の通りである。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
ペレットの外方に中継用導体を配設するとともに、この
導体にペレットにおける回路の一部と、リードの一部と
をそれぞれ接続することにより、簡単なリード位置の変
更等のような場合、ペレットにおけるレイアウトを変更
しなくとも済むため、リード位置変更に伴う集積回路に
ついての設計変更の必要性を抑制することができる。By arranging a relay conductor on the outside of the pellet and connecting a part of the circuit in the pellet and a part of the lead to this conductor, it is possible to easily change the lead position. Since there is no need to change the layout of the integrated circuit, it is possible to suppress the necessity of changing the design of the integrated circuit due to changing the lead position.
第１図は本発明の一実施例であるＦＰＧＩＣを示すキャ
ンプを除いた状態の平面図、
第２図は第１図の■−■線断面に相当する縦断面図、
第３図は作用を説明するための平面図である。
１・・・ベース、２・・・キャビティ、３・・・マウン
ト部、４・・・ペレット、５．５ａ〜５ｄ° ・・・電
極パッド、６．６３〜６ｄ’ ・・・インナリード、
７．７ａ〜７ｄ’ ・・・アウタリード、８．８３〜
８ｄ’ ・・・ボンディングワイヤ、９・・・第１中
継用導体、１０・・・第２中継用導体、１１・・・ガラ
ス封着部、１２・・・キャップ、１３・・・パッケージ
、。
叉−二Fig. 1 is a plan view of an FPGIC that is an embodiment of the present invention with the camp removed; Fig. 2 is a vertical cross-sectional view corresponding to the section taken along the line ■-■ in Fig. 1; and Fig. 3 shows the operation. It is a top view for explanation. DESCRIPTION OF SYMBOLS 1... Base, 2... Cavity, 3... Mount part, 4... Pellet, 5.5a-5d°... Electrode pad, 6.63-6d'... Inner lead,
7.7a~7d'...outer lead, 8.83~
8d'... Bonding wire, 9... First relay conductor, 10... Second relay conductor, 11... Glass sealing part, 12... Cap, 13... Package. chimney two
Claims (1)
の導体にはペレットにおける回路の一部とリードの一部
とがそれぞれ電気的に接続されていることを特徴とする
電子装置。２、中継用導体が、パッケージのガラス封着
部となる部分に配設されていることを特徴とする特許請
求の範囲第１項記載の電子装置。 ３、中継用導体が、銀−パラジウム基合金を用いて形成
されていることを特徴とする特許請求の範囲第１項記載
の電子装置。[Claims] 1. A relay conductor is provided outside the pellet, and a part of the circuit in the pellet and a part of the lead are electrically connected to this conductor. Featured electronic devices. 2. The electronic device according to claim 1, wherein the relay conductor is disposed at a portion of the package that is to be sealed with glass. 3. The electronic device according to claim 1, wherein the relay conductor is formed using a silver-palladium based alloy.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61123400A JPS62281436A (en) | 1986-05-30 | 1986-05-30 | Electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61123400A JPS62281436A (en) | 1986-05-30 | 1986-05-30 | Electronic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62281436A true JPS62281436A (en) | 1987-12-07 |
Family
ID=14859616
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61123400A Pending JPS62281436A (en) | 1986-05-30 | 1986-05-30 | Electronic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62281436A (en) |
-
1986
- 1986-05-30 JP JP61123400A patent/JPS62281436A/en active Pending
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