JPS5949695B2 - Manufacturing method for glass-sealed semiconductor devices - Google Patents

Manufacturing method for glass-sealed semiconductor devices

Info

Publication number
JPS5949695B2
JPS5949695B2 JP15091476A JP15091476A JPS5949695B2 JP S5949695 B2 JPS5949695 B2 JP S5949695B2 JP 15091476 A JP15091476 A JP 15091476A JP 15091476 A JP15091476 A JP 15091476A JP S5949695 B2 JPS5949695 B2 JP S5949695B2
Authority
JP
Japan
Prior art keywords
cavity
glass
base member
cap member
sealing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP15091476A
Other languages
Japanese (ja)
Other versions
JPS5375859A (en
Inventor
俊二 小池
元 村上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15091476A priority Critical patent/JPS5949695B2/en
Publication of JPS5375859A publication Critical patent/JPS5375859A/en
Publication of JPS5949695B2 publication Critical patent/JPS5949695B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Description

【発明の詳細な説明】 本発明は、例えばデュアル・イン・ライン型IC(集積
回路)装置のようなガラス封止半導体装置に関し、特に
そのパッケージ構造の改良に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a glass-sealed semiconductor device, such as a dual-in-line IC (integrated circuit) device, and particularly to improvements in its package structure.

従来提案されているデュアル・イン・ライン型IC装置
においては、セラミックベース部材の表面に設けたキャ
ビティ内にICチップを固着するとともにそのキャビテ
ィ周辺部にリードを取付け、その上にセラミックキャッ
プ部材を重ねてその重ね合せ部をガラスで封止するよう
になつている。
In conventionally proposed dual-in-line IC devices, an IC chip is fixed in a cavity provided on the surface of a ceramic base member, leads are attached around the cavity, and a ceramic cap member is placed on top of the lead. The overlapped portion is then sealed with glass.

この場合、キャップ部材にはベース部材のキヤビつ テ
イより大きなキャビティが形成されているので、キャッ
プ部材のキャビティ周辺部とベース部材のキャビティ周
辺部とを重ね合わせると、引出しリードの内方端部はキ
ャップ部材のキャビティ内に露呈する形になる。このた
め、ICチップの所定5 の電極をボンディングワイヤ
により対応するリードの内方端部に結線すれば、キャッ
プ部材をベース部材に重ねてその重ね合せ部をガラス封
止する際、ボンディングワイヤのリードヘのボンディン
グ部は重ね合せ部(すなわちガラス封止部)から0 外
れてキャビティ内に位置するようになり、ワイヤがキャ
ップ部材に接触することはないのでワイヤの断線事故を
生ずるようなことは殆んどない。このように、従来のパ
ッケージ構造は、それ自体かなり満足な性能を示すもの
であるが、内部に5収納すべき半導体チップ(特にIC
チップ)が大型化した場合、これに対処するにはそれ相
当にパッケージを構成するベース部材及びキャップ部材
のサイズを大きくしなければならないという不都合があ
る。すなわち、チップサイズの増大に対しo てパッケ
ージサイズをそれ相応に大きくすることは、パッケージ
製作設備の変更やパッケージ原価の向上につながり好ま
しいことではない。本発明の目的は、上記した従来技術
の問題点を解決した新規なパッケージ構造をそなえたガ
ラス5 封止半導体装置を提供することにある。
In this case, since the cap member has a cavity that is larger than the cavity of the base member, when the periphery of the cavity of the cap member and the periphery of the cavity of the base member are overlapped, the inner end of the drawer lead is It is exposed within the cavity of the cap member. Therefore, if five predetermined electrodes of an IC chip are connected to the inner ends of the corresponding leads using bonding wires, when the cap member is stacked on the base member and the overlapped portion is sealed with glass, the leads of the bonding wires can be connected to the inner ends of the corresponding leads using bonding wires. The bonding part is removed from the overlapping part (that is, the glass sealing part) and is located inside the cavity, and the wire does not come into contact with the cap member, so there is almost no chance of wire breakage. Who? As described above, the conventional package structure shows fairly satisfactory performance in itself, but it is difficult to accommodate the semiconductor chips (especially ICs) that must be housed inside.
When the size of chips (chips) increases, there is a problem in that the size of the base member and cap member that constitute the package must be correspondingly increased in order to cope with this increase. That is, increasing the package size commensurately with the increase in chip size is not desirable because it leads to changes in package manufacturing equipment and increases in package cost. An object of the present invention is to provide a glass-sealed semiconductor device having a novel package structure that solves the problems of the prior art described above.

本発明の特徴の1つは、パッケージ全体の大きさをその
ままとしておいて内部キャビティの大きさをチツプサイ
ズに応じて大きくする点にある。
One of the features of the present invention is that the size of the internal cavity is increased in accordance with the chip size while keeping the overall size of the package unchanged.

具体的には、半導体チツプを収納すべきベース部材のキ
ヤビテイをキヤツプ部材のキヤビテイ程度にまで大きく
するとともに、一端が半導体チツプに接続された接続用
ワイヤの他端と引出しリードの内方端部とのボンデイン
グをガラス封止予定位置で行うようにする。このように
すると、キヤツプ部材をベース部材に重ね合せ、その間
をガラス封止する際に、キヤツプ部材が接続ワイヤに接
触して断線事故を誘発させるように考えられやすいが、
本願発明者の研究によれば、そのような事故は予期に反
して多くなく、また、若干の製法上の工夫でほとんど回
避しうることが明らかにされた。次に、添付図面に示す
実施例について本発明を説明する。第1図は、本発明の
一実施例によるデユアル・イン・ライン型1C装置の断
面を示すものである。
Specifically, the cavity of the base member in which the semiconductor chip is to be housed is made as large as the cavity of the cap member, and one end of the connecting wire is connected to the semiconductor chip, and the other end of the connecting wire is connected to the inner end of the drawer lead. Bonding should be performed at the location where glass sealing is planned. In this case, when the cap member is stacked on the base member and the space between them is sealed with glass, it is likely that the cap member will come into contact with the connecting wire and cause a disconnection accident.
According to the research conducted by the present inventors, it has been found that such accidents are not as common as expected, and that most of them can be avoided by making some improvements in the manufacturing process. The invention will now be described with reference to embodiments shown in the accompanying drawings. FIG. 1 shows a cross section of a dual-in-line type 1C device according to an embodiment of the present invention.

同図において、10はキヤビテイ10aを有するセラミ
ツクベース部材、20はキヤビテイ20aを有するセラ
ミツクキヤツプ部材であり、キヤツプ部材20のキヤビ
テイ周辺部の下面には封止用ガラス突起22がところど
ころに付着されている。ベース部材10のキヤビテイ周
辺部上面には、リード16が紙面に垂直な方向に多数本
直線状に並設されており、キヤビテイ10a内には接着
層12によりICチツプ14が固着されている。キヤビ
テイ10aはキャビテイ20aとほぼ同一の大きさに形
成されており、リード16の内方端部は直接これらキヤ
ビテイ内に延長していない。このため、チツプ14に一
端がボンデイングされた例えばAl製の接続ワイヤ18
の他端は、キヤツプ部材20のキヤビテイ周辺部とベー
ス部材10のキヤビテイ周辺部との間、すなわちガラス
封止されるべき部分間において図示の位置でリード16
の内方端部にボンデイングされる。ガラス封止を行う場
合には、まずキヤツプ部材20をベース部材10上に重
ね合せる。
In the figure, 10 is a ceramic base member having a cavity 10a, 20 is a ceramic cap member having a cavity 20a, and sealing glass protrusions 22 are attached here and there to the lower surface of the periphery of the cavity of the cap member 20. . A large number of leads 16 are linearly arranged in a direction perpendicular to the paper on the upper surface of the base member 10 around the cavity, and an IC chip 14 is fixed in the cavity 10a by an adhesive layer 12. Cavity 10a is formed to be approximately the same size as cavity 20a, and the inner ends of leads 16 do not extend directly into these cavities. For this purpose, a connecting wire 18 made of, for example, Al and having one end bonded to the chip 14 is used.
The other end is connected to the lead 16 at the illustrated position between the cavity periphery of the cap member 20 and the cavity periphery of the base member 10, that is, between the portions to be glass-sealed.
bonded to the inner end of the When performing glass sealing, the cap member 20 is first placed on the base member 10.

この場合、封止用ガラス突起22をワイヤ18に接触し
ない位置にところどころ設けてあるので、断線事故は殆
んど発生しない。この後、適当な熱処理によりガラス突
起22を溶融させ封止予定部分に全面的に拡延させ、し
かる後固化させると、所望の気密的ガラス封止が達成さ
れる。この結果、ワイヤ18はリード16の近傍部分に
おいてガラス封止層中に埋めこまれた形になる。上記し
たように本発明によれば、キヤビテイ10aの大きさを
変更するという簡単な手段によつてパツケージ原価の低
減を達成することができ、その上、封着作業が先立つて
封止用ガラスの配置に若干の工夫をほどこすだけで、ボ
ンデイングワイヤの断線を軽減することができるなど多
くの実益が得られる。
In this case, since the sealing glass protrusions 22 are provided in places where they do not come into contact with the wire 18, disconnection accidents hardly occur. Thereafter, the glass protrusions 22 are melted and spread over the entire area to be sealed by a suitable heat treatment, and then solidified to achieve the desired airtight glass sealing. As a result, the wire 18 is embedded in the glass sealing layer in the vicinity of the lead 16. As described above, according to the present invention, it is possible to reduce the package cost by simply changing the size of the cavity 10a. By making a few changes to the arrangement, many practical benefits can be obtained, such as reducing bonding wire breakage.

本発明によれば、ベース部材の周辺部は突出した壁部を
有しており、ワイヤ18の他端は、この壁部突出面に取
付されたリード16にワイヤボンデイングされ、これに
よつて、ボンデイングワイヤの他端は半導体ペレツトの
周辺部より常に高い位置に配設されることとなるから、
ボンデイングワイヤの他端が半導体ペレツトの周辺部に
短絡するという好しくない事故は防止される。
According to the present invention, the peripheral portion of the base member has a protruding wall, and the other end of the wire 18 is wire bonded to the lead 16 attached to the protruding surface of the wall. Since the other end of the bonding wire is always placed at a higher position than the peripheral part of the semiconductor pellet,
An undesirable accident in which the other end of the bonding wire shorts to the periphery of the semiconductor pellet is prevented.

なお、上記実施例において、断線防止策としては封止ガ
ラスを突起状に設けるやり方を例示したが、これ以外に
も種々のやり方があり、上記実施例に限定されることは
ない。
In addition, in the above-mentioned embodiment, a method of providing the sealing glass in a protruding shape was exemplified as a measure to prevent disconnection, but there are various other methods, and the method is not limited to the above-mentioned embodiment.

例えば、リード16に突起を設け封止ガラスにより封止
することも考えられる。
For example, it is also conceivable to provide a protrusion on the lead 16 and seal it with sealing glass.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の一実施例によるIC装置の一製造工
程における断面図、第2図は、第1図の装置のキヤツプ
部材を下面からみた場合の平面図である。 符号の説明、10・・・・・・ベース部材、12・・・
・・・接着層、14・・・・・・ICチツプ、16・・
・・・・リード、18・・・・・・接続ワイヤ、20・
・・・・・キヤツプ部材、22・・・・・・封止用ガラ
ス突起。
FIG. 1 is a cross-sectional view of one manufacturing process of an IC device according to an embodiment of the present invention, and FIG. 2 is a plan view of the cap member of the device of FIG. 1 viewed from below. Explanation of symbols, 10...Base member, 12...
...Adhesive layer, 14...IC chip, 16...
...Lead, 18...Connection wire, 20.
... Cap member, 22 ... Glass protrusion for sealing.

Claims (1)

【特許請求の範囲】[Claims] 1 底部と、該底部の周辺において突出している壁部と
によつてキャビティを規定するように形成されたベース
部材を用意し、該ベース部材のキャビティ内に半導体チ
ップを固着するとともに、前記壁部突出面に予め形成さ
れたリードと、前記半導体チップとの間を電気的に接続
するこめに、これら両者に金属ワイヤをボンディングし
、前記壁部突出面に対応して予め所定間隔を以て形成さ
れた複数の封止用ガラス突起部を有するキャップ部材を
前記ベース部材に重ね合せて熱処理することによつて、
前記封止用ガラ又突起部を前記壁部突出面で溶融させ、
前記ベース部材と前記キャップ部材とを封止することを
特徴とするガラス封止半導体装置の製法。
1. Prepare a base member formed to define a cavity by a bottom part and a wall part protruding around the bottom part, fix a semiconductor chip in the cavity of the base member, and fix the semiconductor chip in the cavity of the base member. Metal wires are bonded to leads preformed on the protruding surface and the semiconductor chip to electrically connect them, and are formed at predetermined intervals in correspondence with the protruding surface of the wall. By superimposing a cap member having a plurality of sealing glass protrusions on the base member and heat-treating the same,
melting the sealing glass or protrusion on the protruding surface of the wall;
A method for manufacturing a glass-sealed semiconductor device, comprising sealing the base member and the cap member.
JP15091476A 1976-12-17 1976-12-17 Manufacturing method for glass-sealed semiconductor devices Expired JPS5949695B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15091476A JPS5949695B2 (en) 1976-12-17 1976-12-17 Manufacturing method for glass-sealed semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15091476A JPS5949695B2 (en) 1976-12-17 1976-12-17 Manufacturing method for glass-sealed semiconductor devices

Publications (2)

Publication Number Publication Date
JPS5375859A JPS5375859A (en) 1978-07-05
JPS5949695B2 true JPS5949695B2 (en) 1984-12-04

Family

ID=15507143

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15091476A Expired JPS5949695B2 (en) 1976-12-17 1976-12-17 Manufacturing method for glass-sealed semiconductor devices

Country Status (1)

Country Link
JP (1) JPS5949695B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4908086A (en) * 1985-06-24 1990-03-13 National Semiconductor Corporation Low-cost semiconductor device package process
JPH02127039U (en) * 1989-03-29 1990-10-19
US5223851A (en) 1991-06-05 1993-06-29 Trovan Limited Apparatus for facilitating interconnection of antenna lead wires to an integrated circuit and encapsulating the assembly to form an improved miniature transponder device

Also Published As

Publication number Publication date
JPS5375859A (en) 1978-07-05

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