JPS62274662A - Ｍｉｓ型半導体装置 - Google Patents

Ｍｉｓ型半導体装置

Info

Publication number
JPS62274662A
JPS62274662A JP11774286A JP11774286A JPS62274662A JP S62274662 A JPS62274662 A JP S62274662A JP 11774286 A JP11774286 A JP 11774286A JP 11774286 A JP11774286 A JP 11774286A JP S62274662 A JPS62274662 A JP S62274662A
Authority
JP
Japan
Prior art keywords
semiconductor device
type semiconductor
gate
insulating film
mis type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11774286A
Other languages
English (en)
Inventor
Seiichi Iwamatsu
誠一 岩松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP11774286A priority Critical patent/JPS62274662A/ja
Publication of JPS62274662A publication Critical patent/JPS62274662A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 ３、発明の詳細な説明 〔産業上の利用分野〕 本発明はＭＩＳ型半導体装置の構造に関する。
〔従来の技術〕
従来、ＭＩＳＩ半導体装看は第２図に示す如き構造をと
るのが通例であった。すなわち、Ｓｉ基板１１の一定表
面にゲート絶縁！１１１４とゲート電極１５を形成し、
該ゲート部両端にソース１２及びドレイン１３の不純物
拡散層領域６Ｓ形成されて成る。
〔発明Ｍ”−解決しようとする問題点〕しかし、上記従
来技術によると、ゲート領域が半導体基板の一定表面に
の入形成される為、高速化を計るのに大酊積を要し、集
積度の向上が計れない等の問題点があった。
本発明は、かかる従来技術の問題点をなくし、高速且つ
集積度の犬なるＭＩＳ型ＦＫＴの構造を提供する事を目
的とする。
〔問題点を解決する之めの手段〕
上記問題点な解決する為に、本発明はＭＩＢ型半導体装
置のゲート領域を一定Ｗｆｆｉに限定せず、全面にボ状
に形成する手段を用いろ事を基本とする。
〔実施例〕
以下、実施例により本発明を詳述する。
第１図は本発明の実施例を示すＭ工８型半導体装置の模
式図である。すなわち、ＳＺ基板１の全表面にわたって
ゲート絶縁膜４とゲート電＄５が形成され、該ゲート領
域の両端にけソース２、ト°しイン３の不純物拡散領域
が形成されて成る。
本発明恍￥１８型半導体装置′）″ならずＭｌｆｉｓ（
Ｍｅｔａｌ　Ｚ１ｇ６ｔｒｏｄｅ　Ｆ３ｅｍｉｃｏｒｄ
ｕｃｔｏｒ　）　ＨＡ半導体装置や：ｒｗｎｅｔｉｏｎ
　Ｆ　Ｋ　Ｔ等のゲート領域を環状に形成すると云う形
で適用できることは云うまでもない。
〔発明の効果〕
本発明の如く、ゲート領域を半導体基板の一定表面く限
らず、仙の定表面にも環状に形成する事により、高速且
つ高集積のＦＩＣＴを形成することができる効果ｂ；あ
る。
【図面の簡単な説明】
ｆ＄１図は本発明の実施例を示すＭＩｉ９型半導体装置
の模式図。 第２図は、従来技術によるＭＩＳ型半導体装置の模式図
を示す。 １．１１・・・・・・５ｆｆｌ基板 ２．１２・・・・・・ソース ３．１３・・・・・・ドレイン ４．１４・・・・・・ゲート絶縁膜 ５　、　１５　・・・・・・　ゲ　−　　ト　ｔ　伺に
以　　上

Claims (1)

    【特許請求の範囲】
  1. 半導体基板表面には環状にゲート絶縁膜が形成され、該
    ゲート絶縁膜上には、やはり環状にゲート電極が形成さ
    れて成る事を特徴とするＭＩＳ型半導体装置。
JP11774286A 1986-05-22 1986-05-22 Ｍｉｓ型半導体装置 Pending JPS62274662A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11774286A JPS62274662A (ja) 1986-05-22 1986-05-22 Ｍｉｓ型半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11774286A JPS62274662A (ja) 1986-05-22 1986-05-22 Ｍｉｓ型半導体装置

Publications (1)

Publication Number Publication Date
JPS62274662A true JPS62274662A (ja) 1987-11-28

Family

ID=14719179

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11774286A Pending JPS62274662A (ja) 1986-05-22 1986-05-22 Ｍｉｓ型半導体装置

Country Status (1)

Country Link
JP (1) JPS62274662A (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5493130A (en) * 1993-06-10 1996-02-20 Micron Technology, Inc. Integrated circuitry having an electrically conductive sidewall link positioned over and electrically interconnecting respective outer sidewalls of two conductive layers
US5736437A (en) * 1993-05-12 1998-04-07 Micron Technology, Inc. Method of fabricating a bottom and top gated thin film transistor having an electrical sidewall connection
US5801397A (en) * 1994-09-30 1998-09-01 Sgs-Thomson Microelectronics, Inc. Device having a self-aligned gate electrode wrapped around the channel
US6291863B1 (en) * 1992-07-01 2001-09-18 Hyundai Electronics Industries Co., Ltd. Thin film transistor having a multi-layer stacked channel and its manufacturing method

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6291863B1 (en) * 1992-07-01 2001-09-18 Hyundai Electronics Industries Co., Ltd. Thin film transistor having a multi-layer stacked channel and its manufacturing method
US5736437A (en) * 1993-05-12 1998-04-07 Micron Technology, Inc. Method of fabricating a bottom and top gated thin film transistor having an electrical sidewall connection
US6229212B1 (en) 1993-05-12 2001-05-08 Micron Technology, Inc. Integrated circuitry and thin film transistors
US6306696B1 (en) 1993-05-12 2001-10-23 Micron Technology, Inc. Methods of forming integrated circuitry methods of forming thin film transistors, integrated circuitry and thin film transistors
US6479332B2 (en) 1993-05-12 2002-11-12 Micron Technology, Inc. Methods of forming integrated circuitry
US6689649B2 (en) 1993-05-12 2004-02-10 Micron Technology, Inc. Methods of forming transistors
US6759285B2 (en) 1993-05-12 2004-07-06 Micron Technology, Inc. Methods of forming transistors
US5493130A (en) * 1993-06-10 1996-02-20 Micron Technology, Inc. Integrated circuitry having an electrically conductive sidewall link positioned over and electrically interconnecting respective outer sidewalls of two conductive layers
US5801397A (en) * 1994-09-30 1998-09-01 Sgs-Thomson Microelectronics, Inc. Device having a self-aligned gate electrode wrapped around the channel

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