JPS62271493A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62271493A JPS62271493A JP61113523A JP11352386A JPS62271493A JP S62271493 A JPS62271493 A JP S62271493A JP 61113523 A JP61113523 A JP 61113523A JP 11352386 A JP11352386 A JP 11352386A JP S62271493 A JPS62271493 A JP S62271493A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- semiconductor device
- substrate
- conductive pattern
- double
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 28
- 239000000758 substrate Substances 0.000 claims description 71
- 238000004080 punching Methods 0.000 claims description 5
- 238000009713 electroplating Methods 0.000 claims description 2
- 238000000465 moulding Methods 0.000 claims 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 11
- 238000007747 plating Methods 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 239000011889 copper foil Substances 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 230000006386 memory function Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 206010052128 Glare Diseases 0.000 description 1
- BZHJMEDXRYGGRV-UHFFFAOYSA-N Vinyl chloride Chemical compound ClC=C BZHJMEDXRYGGRV-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000004313 glare Effects 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
Landscapes
- Credit Cards Or The Like (AREA)
- Structure Of Printed Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
３、発明の詳細な説明
〔産業上の利用分野〕
本発明は、ＩＣカードやＩＣカートリッジなどに適用さ
れる極薄形の半導体装置に係り、特にこの種半導体装！
の回路基板に好適な両面電解めっき基板に関する。[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an ultra-thin semiconductor device applied to IC cards, IC cartridges, etc., and particularly to this type of semiconductor device!
The present invention relates to a double-sided electrolytic plated substrate suitable for use as a circuit board.
近年、ＩＣ化されたデータ処理部とｈｃ化されたメモリ
とを有するＩＣカードを用いて商品取引や預貯金、それ
に個人情報の記録などを行うようにしたシステムが注目
さ九でいる。In recent years, systems that use IC cards that have an IC data processing unit and an HC memory to perform product transactions, deposits and savings, and record personal information have been attracting attention.
第７図はかかるシステムに使用されるＩＣカードの慨略
を示す平面図であって、２１はカード本体、２１ａは暗
証記号などを記録する磁気ストライプ、２１ｂはエンボ
スエリア、２３はデータ処理機能及びメモリ機能を有す
る２つのＩＣチップ２２．２２ａを搭載した半導体装置
を示している。FIG. 7 is a plan view schematically showing an IC card used in such a system, in which 21 is the card body, 21a is a magnetic stripe for recording a password, 21b is an embossed area, 23 is a data processing function and the like. It shows a semiconductor device equipped with two IC chips 22 and 22a having a memory function.
上記半導体装置２３は、第７図及び第８図に示すように
、上記カード本体２１の表面の上記磁気ストライプ２１
ａとエンボスエリア２１ｂの中間領域に設けられた痛み
２１ｃ内に嵌め込まれ、接着剤２５によって接着される
。上記半導体装Ｗｔ２３は、第７図及び第９図に示すよ
うに１表面にｆＩ！源印加、データ入出力、クロック入
力、接地などのだめの８個の外部端子２４１〜２４θが
形成された外部端子用基板２３ａと、片面に所要の配線
パターン２７が形成された配線用基板２３ｂとが接着剤
２６を介して積層された回路基板を有する。As shown in FIGS. 7 and 8, the semiconductor device 23 includes the magnetic stripe 21 on the surface of the card body 21.
The embossed area 21c is fitted into the groove 21c provided in the middle area between the embossed area 21b and the embossed area 21b, and is bonded with an adhesive 25. The semiconductor device Wt23 has fI! on one surface as shown in FIGS. 7 and 9. An external terminal board 23a is formed with eight external terminals 241 to 24θ for power application, data input/output, clock input, grounding, etc., and a wiring board 23b is formed with a required wiring pattern 27 on one side. It has circuit boards laminated with an adhesive 26 in between.
上記２つのＩＣ，チップ２２．２２ａは、第９図に示す
ように、上記外部端子用基板２３ａの裏面に接着され、
これら２つのＩＣチップ２２１２２ａの端子電極と上記
配線パターン２７との間をボンディングワイヤ２９にて
接続したのち、上記ＩＣチップ２２ｓ ２２ ａを取り
囲むように配置された枠体２８の内部に封止樹脂３０を
充填して封止される。The two ICs and chips 22 and 22a are bonded to the back surface of the external terminal board 23a, as shown in FIG.
After connecting the terminal electrodes of these two IC chips 22122a and the wiring pattern 27 with bonding wires 29, a sealing resin 30 is placed inside a frame 28 arranged so as to surround the IC chips 22s and 22a. is filled and sealed.
上記した従来のＩＣカードに適用される半導体装置２３
は、データ処理機能を有するＩＣチップ２２及びメモリ
機能を有するＩＣチップ２２δを搭載しているため配線
パターンが長大かつ複雑になり、上記したように回路基
板を外部端子用基板２３ａと配線用基板２３ｂから成る
２Ｍ！ｉｔ造にしなくてはならず、さらに回路基板の平
面積も大型化する。然るに、上記カード本体２１は厚さ
が約０．８ｍｍ程度の塩化ビニル等で形成され可撓性を
有するものであるから、回路基板の平面積が大きいとカ
ード本体２１が曲げられた際に回路基板の受ける曲げ応
力が大きくなり１回路基板、ひいてはＩＣチップ２２．
２２ａの破損という重大な不具合を生ずる虞九が高い。Semiconductor device 23 applied to the above conventional IC card
is equipped with an IC chip 22 having a data processing function and an IC chip 22δ having a memory function, so the wiring pattern becomes long and complicated, and as described above, the circuit board is divided into an external terminal board 23a and a wiring board 23b. 2M consisting of! It must be constructed using IT, and the planar area of the circuit board also increases. However, since the card body 21 is made of vinyl chloride or the like with a thickness of approximately 0.8 mm and is flexible, if the planar area of the circuit board is large, the circuit may be damaged when the card body 21 is bent. The bending stress that the board receives increases, causing damage to the 1 circuit board and eventually the IC chip 22.
There is a high possibility that a serious problem such as damage to 22a will occur.
かかる問題を解決するため、データ処理機能とメモリ機
能を併有するＩＣチップが開発された。In order to solve this problem, an IC chip that has both a data processing function and a memory function has been developed.
このＩＣチップを使用すると、ＩＣチップの数が１つで
あるため回路基板に形成すべき配線パターンが格段に短
縮イヒ、簡略化される。そこで、回路基板として従来の
ように外部端子用基ＦＡ２３ ａと配線用基板２３ｂと
を′Ｕｉ層して成る回路基板に代えて、１枚の絶縁基板
の表裏両面に外部端子及び所要の配線パターンを電解め
っきして成る回路基＠を適用することが可能となる。し
かしながら、かかる両面電解めっき基板は、実際の製造
に当って、以下の如き問題点があることがヤ」明した。When this IC chip is used, since the number of IC chips is one, the wiring pattern to be formed on the circuit board can be significantly shortened and simplified. Therefore, instead of using a conventional circuit board consisting of an external terminal board FA23a and a wiring board 23b in 'Ui layers, external terminals and required wiring patterns are formed on both the front and back sides of a single insulating board. It becomes possible to apply a circuit board made by electroplating. However, it has been found that such double-sided electrolytically plated substrates have the following problems when actually manufactured.
以下、両面ｆｆｉ解めっき基板の製造方法及びこれによ
って形成される導電パターンの一例を第１０図（ａ）〜
（ｈ）、第１１図及び第１２図に基づいて説明する。Below, an example of a method for manufacturing a double-sided FFI plated substrate and a conductive pattern formed thereby is shown in FIGS.
(h), will be explained based on FIGS. 11 and 12.
まず、第１０図（ａ）に示すように、所定形状の導電パ
ターンを複数個形成可能な面積を有する絶Ｓ基板３１の
表裏両面の全域に、銅箔３２，３２ａを略均−の厚さに
ラミネートする。First, as shown in FIG. 10(a), copper foils 32, 32a are spread to a substantially uniform thickness over the entire front and back surfaces of an insulated substrate 31, which has an area on which a plurality of conductive patterns of a predetermined shape can be formed. Laminate on.
次いで、第１Ｏ図（ｂ）に示すように、所定の位置に上
記銅箔３２から銅箔３２ａに貫通する透孔３３を穿設す
る。Next, as shown in FIG. 1O(b), a through hole 33 penetrating from the copper foil 32 to the copper foil 32a is bored at a predetermined position.
次いで、第１Ｏ図（ｃ）に示すように、上記透孔３３が
穿設された絶縁基板３１に無電解めっきを施し、上記銅
箔３２，３２ａの表面及び上記透孔３３の内面に銅の薄
膜３４を形成する。Next, as shown in FIG. 1O(c), electroless plating is applied to the insulating substrate 31 in which the through hole 33 is formed, and copper is applied to the surfaces of the copper foils 32, 32a and the inner surface of the through hole 33. A thin film 34 is formed.
次いで、第１０図（ｄ）に示すように、上記銅の薄膜３
４を電極として銅を電解めっきし、所定の厚さの銅めっ
き層３５及びこれに連なるスルーホール３６を形成する
。Next, as shown in FIG. 10(d), the copper thin film 3 is
4 as an electrode, copper is electrolytically plated to form a copper plating layer 35 of a predetermined thickness and a through hole 36 connected thereto.
次いで、第１０図（ｅ）に示すように、上記絶縁基板３
１の銅めっき店３５の表面にホトレジスト３７を略均−
の厚さに塗布する。Next, as shown in FIG. 10(e), the insulating substrate 3
Approximately uniform photoresist 37 is applied to the surface of the copper plating shop 35 of No. 1.
Apply to a thickness of .
次いで、第１０図（ｆ）に示すように、ホトレジスト層
３７の表面に所要とする配線パターンと同一のパターン
に形成されたマスク３８を被着し。Next, as shown in FIG. 10(f), a mask 38 formed in the same pattern as the desired wiring pattern is applied to the surface of the photoresist layer 37.
該マスク３８が被覆されていない部分に光３８ａを照射
してを露光する。The portions not covered by the mask 38 are exposed by irradiating the light 38a.
次いで、上記マスク３８を除去したのち、上記露光部み
ホトレジストを現像処理して露光部分のホトレジスト３
７を除去し、さらに、上記現像済みホトレジストを有す
る絶縁基板３１をエツチング液に浸して、上記ホトレジ
スト３７が除去された部分（７）ｔｊｌｆｆｉ （鋼！
３２．３２ａ、 ｗ１１１１３４． 及び銅めっき層３
５）を除去する。これによって。Next, after removing the mask 38, the photoresist in the exposed area is developed to form the photoresist 3 in the exposed area.
7 is removed, and further, the insulating substrate 31 having the developed photoresist is immersed in an etching solution, and the portion (7) from which the photoresist 37 is removed is removed.
32.32a, w111134. and copper plating layer 3
5) Remove. by this.
絶縁基板３１の表面に第１１図に示す如き所定の配線パ
ターン３９及びめっきり−ド４０とを形成すると共に、
絶縁基板３１の裏面に第１２図に示す如き上記外部端子
２４１〜２４＠と略同形のパターン４１を形成する。While forming a predetermined wiring pattern 39 and a clear line 40 as shown in FIG. 11 on the surface of the insulating substrate 31,
On the back surface of the insulating substrate 31, a pattern 41 having substantially the same shape as the external terminals 241 to 24@ as shown in FIG. 12 is formed.
次いで、上記めっきり−ド４０の一端をめっき装置の陰
極に接続し、第１０図（ｇ）に示すように。Next, one end of the plate 40 was connected to the cathode of the plating apparatus, as shown in FIG. 10(g).
上記銅めっき層３５の表面にニッケルめっき層４２及び
金めつき層４３を順次積層して、スルーホール３６を介
して接続された絶縁基板３１の表裏両面の導電パターン
（配線パターン３９及び外部ｆｉｌ！パターン４１）を
−組とする複数組の導電パターンが互いにめっきり−ド
４０を介して接続された基板シート４４を形成する。A nickel plating layer 42 and a gold plating layer 43 are sequentially laminated on the surface of the copper plating layer 35, and conductive patterns (wiring pattern 39 and external film! A plurality of sets of conductive patterns including pattern 41) are clearly connected to each other via leads 40 to form a substrate sheet 44.
最後に、第１０図（ｈ）に示すように、上記基板シート
４４から、配線パターン３９の外周部を打ち抜いて、所
要とする両面電解めっき基板４５を取り出す。Finally, as shown in FIG. 10(h), the outer periphery of the wiring pattern 39 is punched out from the substrate sheet 44 to take out the required double-sided electroplated substrate 45.
上記のような！１１造方法を採用した場合、基板シート
４４から両面電解めっき基板４５を取り出すためには、
めっきり−ド４０を切断しなくてはならず、切断部に上
記めっきり−ド４０のパリを生ずる。上記絶縁基板３１
は、厚さが約Ｑ、１ｍｍ乃至１ ｍ ｍ ８度のガラス
繊維混入エポキシ板によって形成されるため、切断部に
まで絶縁基板３１の裏面側に形成された外部電極パター
ン４１が形成されていると、第１３図に示すように、め
っきリード４０から引き出されたバリ４６が絶縁基板３
１を介して絶縁された裏面の外部電極パターン４１と短
絡するといった不具合を生じる。このため、製品の歩留
りが悪く、また、個々の両面電解めっき基板について打
ち抜き後上記のバリ４６を除去する加工を施すときには
、生産性が低下し製造コストが高騰するといった問題を
惹起することになる。尚、逆に、基板シート４４の外部
！！＃！ｉパターン４１側から打ち抜き加工を行った場
合には。Like above! When the manufacturing method No. 11 is adopted, in order to take out the double-sided electrolytic plated substrate 45 from the substrate sheet 44,
The blade 40 must be cut sharply, resulting in a break in the blade 40 at the cut portion. The insulating substrate 31
is formed of a glass fiber mixed epoxy plate with a thickness of approximately Q, 1 mm to 1 mm 8 degrees, so that the external electrode pattern 41 formed on the back side of the insulating substrate 31 is formed even at the cut portion. Then, as shown in FIG.
This may cause a short circuit with the external electrode pattern 41 on the back surface which is insulated via 1. For this reason, the yield of the product is poor, and when processing is performed to remove the burrs 46 mentioned above after punching each double-sided electrolytic plated substrate, this causes problems such as a decrease in productivity and a rise in manufacturing costs. . In addition, on the contrary, the outside of the substrate sheet 44! ! #! When punching is performed from the i-pattern 41 side.
外部電極パターン４１の打ち抜き部分からパリを生じ、
これがめつきり−ド４０と短絡して上記と同様の問題を
生ずる。A crack is generated from the punched portion of the external electrode pattern 41,
This causes a short circuit with the plating board 40, causing the same problem as described above.
本発明は、上記した従来技術の問題点を解消し、歩留り
が良好で生産性に優れ、かつ短絡などの不具合のない半
導体装置を提供するため、絶縁基板の表裏両面にスルー
ホールを介して接続された２つの導電パターンを電解め
っきし、これら２つの３電パターンのうちいすオしか一
方の８電パターンに咬いて上記絶縁基板の外周縁に延び
るめっきり一ドが形成された両面電解めっき基板を有す
る半導体装置において、上記両面電解めっき基板に形成
される２つの導電パターンのうち、上記めっきリードが
形成されていない導電パターンと上記絶縁基板の外周縁
との間の少なくとも上記めっきリードと対応する位置に
、導電パターンの非形成領域を設けたことを特徴とする
ものである。The present invention solves the problems of the conventional technology described above, and provides a semiconductor device with good yield, excellent productivity, and no defects such as short circuits. The two conductive patterns thus formed are electrolytically plated, and a double-sided electrolytic plated substrate is formed in which one of the two 3-conductor patterns and one of the 8-conductor patterns is formed with a clear line extending to the outer periphery of the insulating substrate. In the semiconductor device, a position corresponding to at least the plated lead between the conductive pattern on which the plated lead is not formed and the outer periphery of the insulating substrate among the two conductive patterns formed on the double-sided electrolytically plated substrate; The device is characterized in that a region in which no conductive pattern is formed is provided.
第３図は本発明に係る半導体装置が搭載されるＩＣカー
ドの一例を示す平面図であって、従来のカード本体と略
同形同大に形成されたカード本体１１の表面に磁気スト
ライプ１２が形成されており、該磁気ストライプ１２と
干渉しない部分に凹設された窪み１３にデータ処理機能
とメモリ機能を併有するＩＣチップ１４が搭載された半
導体装置１５が嵌め込まれている。FIG. 3 is a plan view showing an example of an IC card in which a semiconductor device according to the present invention is mounted, in which a magnetic stripe 12 is formed on the surface of a card body 11 formed to have approximately the same shape and size as a conventional card body. A semiconductor device 15 mounted with an IC chip 14 having both a data processing function and a memory function is fitted into a recess 13 formed in a portion that does not interfere with the magnetic stripe 12.
第１図は本発明にかかる半導体装＠１５にｉｆＩ用され
る両面電解めっき基板の配線パターン形成面側から見た
平面図、第２図は本発明にかかる両面電解めっき基板の
外部端子形成面側から見た平面図であって、１は両面電
解めっき基板、２は絶縁基板、３は配線パターン、４は
めっきリード、５１〜５１Ｉは外部端子、６１〜６１１
はスルーホールを示す。FIG. 1 is a plan view of a double-sided electrolytically plated substrate used for ifI in a semiconductor device @15 according to the present invention, viewed from the wiring pattern forming side, and FIG. 2 is an external terminal-forming surface of the double-sided electrolytically plated substrate according to the present invention. It is a plan view seen from the side, and 1 is a double-sided electrolytic plated substrate, 2 is an insulating substrate, 3 is a wiring pattern, 4 is a plating lead, 51 to 51I are external terminals, and 61 to 611
indicates a through hole.
配線パターン３は、第１図に示すように、絶縁基板２の
左右側辺部に近接して配設された５個のスルーホール６
１〜６５からＩＣチップ設定部７及びその他所要の位置
に向けて５条のリード端子３１〜３５が形成され、また
、絶縁基板２の略中央部には、絶縁基板２の上辺の近傍
からＩＣチップ設定部７に向けて１条のリード端子３も
が形成されている。As shown in FIG. 1, the wiring pattern 3 includes five through holes 6 arranged close to the left and right sides of the insulating substrate 2.
Five lead terminals 31 to 35 are formed from 1 to 65 toward the IC chip setting section 7 and other required positions, and approximately at the center of the insulating substrate 2, an IC chip is formed from near the upper side of the insulating substrate 2. A single lead terminal 3 is also formed toward the chip setting section 7.
めっきり−ド４は、上記スルーホール６１〜６Ｂ及び上
記絶縁基板２の略中央部に形成されたリード端子３６か
ら絶縁基板２の外周縁にまで延設される。The clear lead 4 extends from the through holes 61 to 6B and the lead terminal 36 formed approximately at the center of the insulating substrate 2 to the outer peripheral edge of the insulating substrate 2.
第２図に示した上記外部端子５１〜５Ｂのうち、５１は
１！源端子、５．！はリセット端子、５３はクロック端
子、５４は接地端子、５５はＩ１０端子。Among the external terminals 51 to 5B shown in FIG. 2, 51 is 1! source terminal, 5. ! is a reset terminal, 53 is a clock terminal, 54 is a ground terminal, and 55 is an I10 terminal.
５６〜５Ｂは予備端子である。これら各外部端子５１〜
５ｓの外側辺は絶縁基板２の外周縁にまで延設されてお
り、上記絶縁基板の表面に形成されためつきり−ド４と
対応する位置に、該めっきリード４よりも幅広の導電パ
ターン非形成部８が設けられている。この導電パターン
非形成部８の深さＳは、任意の大きさに形成可能である
が、余り大きな導電パターン非形成部８を設けると、こ
の両面電解めっき基板１をカード本体１°１の窪み１３
に埋設した場合に製品の美観が劣化するため、０．１ｍ
ｍ乃至０．６ｍｍＰｉ度に形成することが好ましい、ま
た、上記した３つの予何端子５６〜５ｇのうち上記［源
端子５１及び接地端子５４と対向する２つの予備端子５
７〜５８の対向部外面側には、斜面形状の面取り９，９
ａが形成されており、カード本体に組込む際に両面電解
めっき基板１の天地方向を容易に判断できるようにして
、作業性の向上が図られている。56 to 5B are spare terminals. Each of these external terminals 51~
5s extends to the outer periphery of the insulating substrate 2, and a conductive pattern wider than the plated lead 4 is formed at a position corresponding to the plated lead 4 formed on the surface of the insulating substrate. A forming section 8 is provided. The depth S of the conductive pattern-free portion 8 can be formed to any size, but if the conductive pattern-free portion 8 is too large, the double-sided electrolytic plated substrate 1 may be placed in a 1° 1 recess on the card body. 13
The aesthetic appearance of the product will deteriorate if it is buried within 0.1 m.
m to 0.6 mmPi degrees, and among the three preliminary terminals 56 to 5g described above, the two preliminary terminals 5 facing the source terminal 51 and the ground terminal 54
On the outer surface side of the opposing portions 7 to 58, there are chamfers 9, 9 in the form of slopes.
a is formed so that the vertical direction of the double-sided electrolytic plated substrate 1 can be easily determined when it is assembled into the card body, thereby improving workability.
上記両面電解めっき基板１の製造方法は、第１０図（ａ
）〜（ｈ）に示したと全く同様であって、この製造工程
のうちホトレジストＪＷ３７を露光する際（第１０図（
ｆ））、ホトレジスト層３７の表面に所要形状のマスク
３８を被着することによって、所定形状の配線パターン
３、めっきり−ド４、外部端子５１〜５日、それに導電
パターン非形成部を形成することができる。The manufacturing method of the double-sided electroplated substrate 1 is shown in FIG.
) to (h), and when exposing the photoresist JW37 in this manufacturing process (Fig. 10 (
f)) By applying a mask 38 of a desired shape to the surface of the photoresist layer 37, a wiring pattern 3 of a predetermined shape, a clear lead 4, external terminals 51 to 5, and a non-conductive pattern portion are formed thereon. be able to.
上記のように構成された両面電解めっき基板１にＩＣチ
ップを搭載する場合には、第４図に示すように、上記絶
縁基板２のＩＣチップ設定部７にＩＣチップ１４を接着
し、該ＩＣチップ１４の端子ｆ！極と上記リード端子３
１〜３６との間をボンディングワイヤ１６にて接続する
。次いで、上記両面電解めっき基板１上の上記ＩＣチッ
プ１４の周囲に付設された枠体１７の内部に封止樹脂１
８を充填し、上記ＩＣチップ１４及びボンディングワイ
ヤ１６を封止する。これによって１本発明に係る半導体
装Ｗ１１５を形成することができる。以下、ＩＣカード
に搭載するに好適なＩＣチップの使用の一例を掲げろ。When mounting an IC chip on the double-sided electrolytic plated substrate 1 configured as described above, as shown in FIG. Terminal f of chip 14! Pole and above lead terminal 3
1 to 36 are connected by a bonding wire 16. Next, a sealing resin 1 is placed inside a frame 17 attached around the IC chip 14 on the double-sided electrolytic plated substrate 1.
8, and the IC chip 14 and bonding wires 16 are sealed. As a result, a semiconductor device W115 according to the present invention can be formed. Below is an example of the use of an IC chip suitable for mounting on an IC card.
ＣＰＵ；ＣＭＯ３８ビツト
マスクＲＯＭ；３にバイト
ＲＡＭ；１２８バイト
ＥＥＰＲＯＭ；２にバイト
両面電解めっき基板サイズ；１０１０Ｘ１２上記実施例
の半導体装置１５は、絶縁基板２の表裏両面に導電パタ
ーンを形成した両面電解めっき基板１を用いたので、基
板構成の簡略化と小型化とを図ることができる。また、
上記実施例に適用される両面電解めっき基板１は、絶縁
基板２の表裏両面に形成される導電パターンのうち、め
っきり−ド４が形成されていない外部端子５１〜５Ｂの
当該めっきリード形成部と対応する位置に導電パターン
の非形成領域を設けたので、複数組の導電パターンが形
成された基板シートから両面電解めっき基板１の単体を
打ち抜く際に切断部の導電パターンからパリを生じても
、このパリが絶縁基板２を介して反対偏に形成された導
電パターンと短絡するということがない。このため、製
品の不具合発生率を低減して歩留りを向上することがで
き、また、上記パリを除去するための特別な加工を施す
必要がないので、その分生産性を向上することができる
。CPU; CMO 38-bit mask ROM; 3 byte RAM; 128-byte EEPROM; 2 byte double-sided electrolytic plated substrate size; 1010X12 The semiconductor device 15 of the above embodiment is a double-sided electrolytically plated substrate on which conductive patterns are formed on both the front and back sides of the insulating substrate 2. 1 is used, it is possible to simplify and downsize the substrate configuration. Also,
The double-sided electrolytic plated substrate 1 applied to the above-mentioned embodiment has a conductive pattern formed on both the front and back surfaces of the insulating substrate 2, and the plated lead forming portions of the external terminals 51 to 5B on which the leads 4 are not clearly formed. Since regions where conductive patterns are not formed are provided at corresponding positions, even if the conductive patterns at the cut portions cause cracks when punching out a single double-sided electrolytic plated substrate 1 from a substrate sheet on which multiple sets of conductive patterns are formed, There is no possibility that this electrode will be short-circuited with the conductive pattern formed oppositely through the insulating substrate 2. Therefore, it is possible to reduce the occurrence rate of product defects and improve yield, and since there is no need to perform special processing to remove the above-mentioned particles, productivity can be improved accordingly.
尚５上記実施例においては、めっきり−ド４が形成され
ていない外部端子５１〜５１！の上記めっきり−ド４と
対応する位置に、該めっきリード４よりも幅広の導電パ
ターン非形成部８を局部的に設けた点に特徴を有するが
、本発明の要旨はこれに限定さ九ろものではなく、第５
図に示すように。5 In the above embodiment, the external terminals 51 to 51 are not provided with the leads 4 conspicuously. The present invention is characterized in that a conductive pattern-free portion 8 wider than the plated lead 4 is locally provided at a position corresponding to the plated lead 4, but the gist of the present invention is not limited thereto. Not a thing, but a fifth
As shown in the figure.
上記絶縁基板２の外周縁とこの外周縁に対向する各外部
端子５１〜５日の外側辺との間に、略一定の幅を有する
帯状の導電パターン非形成領域８ａを周設することもで
きる。この導電パターンの非形成領域８ａの帽Ｗは、任
意の大きさに形成可能であるが、この両面電解めっき基
板をカード本体の窪みに埋設した場合、該窪みの外周縁
と上記外部端子３１〜３θの外側辺との間に余り大きな
間隙があると製品の美観が劣化するため、０．１ｍｍ乃
至０．６ｍｍＰｉ！度に形成することが好ましし１゜
上記第２実施例の両面電解めっき基板は、上記第１実施
例のもの１と同様の効果を奏するほか。A strip-shaped conductive pattern-free region 8a having a substantially constant width may be provided between the outer peripheral edge of the insulating substrate 2 and the outer side of each of the external terminals 51 to 5 facing the outer peripheral edge. . The cap W in the conductive pattern non-forming area 8a can be formed to any size, but when this double-sided electroplated substrate is buried in a recess of the card body, the cap W in the area 8a where no conductive pattern is formed can be formed between the outer periphery of the recess and the external terminals 31 to 31. If there is an excessively large gap between the outer side of 3θ, the aesthetic appearance of the product will deteriorate, so the gap should be between 0.1mm and 0.6mmPi! The double-sided electrolytic plated substrate of the second embodiment has the same effects as the substrate 1 of the first embodiment.
外部端子３１〜３Ｂの形状がシンプル化され、美観に優
れるという効果がある。The shape of the external terminals 31 to 3B is simplified and has the effect of being aesthetically pleasing.
また、上記各実施例においては、配線パターン３の形成
面にめっきり−ド４を形成し、これと対向する外部端子
５１〜５ｅの形成面に導電パターン非形成部８，８ａを
設けた場合について説明したが１本発明の要旨はこれに
限定されるものではなく、第６ｒ！！Ｉに示すように、
外部端子５１〜５＠の形成面にめっきり−ド４を形成し
、これと対向する配線パターン３の形成面に導電パター
ン非形成部８を設けることも可能である。In each of the above embodiments, the conductive pattern-free portions 8, 8a are provided on the surface where the wiring pattern 3 is formed and the conductive pattern-free portions 8, 8a are formed on the surface where the external terminals 51 to 5e are formed. Although described, the gist of the present invention is not limited to this, and the gist of the present invention is not limited to this. ! As shown in I,
It is also possible to form the conductive pattern 4 clearly on the surface where the external terminals 51 to 5 are formed, and to provide the conductive pattern-free portion 8 on the surface where the wiring pattern 3 is formed opposite thereto.
その他、配線パターン３．めっきり−ド４、及び外部端
子５１〜５ｅの形状、二！しら導電パターンの形成方法
及び材質、それに基板シートから両面電解めっき基板の
単体を取り出す手段等については、上記実施例のもの又
は方法に限定されるものではなく、必要に応じて任意に
設計することができる。Other wiring patterns 3. The shape of the clear card 4 and the external terminals 51 to 5e, 2! The method and material for forming the conductive pattern, the means for taking out the single double-sided electroplated substrate from the substrate sheet, etc. are not limited to the methods or methods of the above embodiments, and may be designed as desired as necessary. Can be done.
さらに、上記各実施例においては１本発明にかかる半導
体装置をＩＣカードに適用する場合を例にとって説明し
たが、本発明の要旨はこれに限定さ、れるものではなく
、その他任意の電子機器に適用可能であることは勿論で
ある。Further, in each of the above embodiments, the case where the semiconductor device according to the present invention is applied to an IC card has been explained as an example, but the gist of the present invention is not limited to this, and can be applied to any other electronic device. Of course, it is applicable.
以上説明したように、本発明の半導体装置は、絶縁基板
の表裏両面に形成される導電パターンのうち、めっきリ
ードが形成されていない外部端子の当該めっきリード形
成部と対応する位置に導電パターンの非形成Ｍ域を設け
た両面電解めっき基板を用いたので、複数組の導電パタ
ーンが形成された基板シートから両面電解めっき基板の
単体を打ち抜く際に切断部の導電パターンからパリを生
じても、二のパリが絶縁基板を介して反対側に形成され
た導電パターンと短絡するということがない、このため
、製品の不具合発生率を低減して歩留りを向上すること
ができ、また、上記パリを除去するための特別な加工を
を施す必要がないので、その分生産性を向上することが
できる。As explained above, in the semiconductor device of the present invention, among the conductive patterns formed on both the front and back surfaces of the insulating substrate, a conductive pattern is formed at a position corresponding to the plated lead forming part of the external terminal where the plated lead is not formed. Since we used a double-sided electrolytically plated substrate with a non-forming M area, even if a single double-sided electrolytically plated substrate is punched out from a substrate sheet on which multiple sets of conductive patterns are formed, burr may occur from the conductive pattern at the cut portion. There is no possibility that the second electrode will short-circuit with the conductive pattern formed on the opposite side of the insulating substrate. Therefore, the incidence of product defects can be reduced and the yield can be improved. Since there is no need to perform special processing for removal, productivity can be improved accordingly.
第１図は本発明の半ＩＪｊ体装置に適用される両面電解
めっき基板の配線パターン形成面側から見た平面図、第
２図は第１図の両面電解めっき基板の外部端子形成面側
から見た平面図、第３図は本発明にかかる半導体装置を
備えたＩＣカードの一例を示す平面図、第４図は本発明
の両面電解めっき基板にＩＣチップを実装した状態を示
す断面図。
第５図は両面電解めっき基板の第２実施例を示す平面図
、第６図は両面電解めっき基板の第３実施例を示す平面
図、第７図は従来知られているＩＣカードの平面図、第
８図は第７図のＩＣカードの半導体装置設定部の断面図
、第９図は従来の半導体装置に適用される回路基板の構
成を示す要部断面図、第１０図（、）〜（ｈ）は両面電
解めっき基板の製造方法を示す工程説明図、第１１＠は
両面電解めっき基板のもとになる基板シートの表面に形
成されるパターンを示す一部破断した平面図、第１２図
は第１１図の基板シートの裏面に形成されるパターンを
示す一部破断した平面図、第１３図は従来の両面電解め
っき基板の問題点を説明する断面図である。
に両面電解めっき基板、２：絶縁基板、３：配線パター
ン、４：めっきリード、５１〜５８：外部端子、６１〜
６８ニスルーボール、７：ＩＣチップ設定部、８．８ａ
：導電パターン非形成部、９．９ａ：面取り、ｌｌ：Ｉ
ｃカード、１２：磁気ストライブ、１３：窪み、１４：
ＩＧチップ。
１５：半導体装置、１６；ボンディングワイヤ、１７：
枠体、）８：封止樹脂
第１図
］ ： 旧：ｈ＋眩角早め、さ基７石叉 ５１
〜５８ 、りＬ壜ｐ搗テ２）話色１ＳＸ才文
６ スｌレーホーｌし３・ Ｄ已線へ°タ
ーン ８゛１１°７−ン卵ｆンＡ１や４゛
洲、でリード
第３図 １〕
１こ ／′
第４ ロ
第５図
第６図
第７図 ２１
第８図
第９図
第１０図
（ａ）
２ａ
（ｂ）
３′２ａ
３′ｌ 立ａ
第１０図
（ｅ）
３フ
ィ
ロ３６
第１０図
第１１図
第１２図
２４＋ ４１ ２１４５３１ ４４１！ｌｒｒどFIG. 1 is a plan view of a double-sided electroplated board applied to the semi-IJJ device of the present invention, viewed from the wiring pattern forming side, and FIG. 2 is a plan view of the double-sided electrolytically plated board of FIG. 1, viewed from the external terminal forming side. FIG. 3 is a plan view showing an example of an IC card equipped with a semiconductor device according to the present invention, and FIG. 4 is a cross-sectional view showing a state in which an IC chip is mounted on a double-sided electroplated substrate of the present invention. FIG. 5 is a plan view showing a second embodiment of a double-sided electroplated substrate, FIG. 6 is a plan view showing a third embodiment of a double-sided electroplated substrate, and FIG. 7 is a plan view of a conventionally known IC card. , FIG. 8 is a sectional view of the semiconductor device setting part of the IC card in FIG. (h) is a process explanatory diagram showing a method for manufacturing a double-sided electrolytic plated substrate, 11th @ is a partially cutaway plan view showing a pattern formed on the surface of a substrate sheet that is the basis of a double-sided electrolytic plated substrate, and 12th The figure is a partially cutaway plan view showing the pattern formed on the back side of the substrate sheet shown in FIG. 11, and FIG. 13 is a cross-sectional view illustrating the problems of the conventional double-sided electrolytic plated substrate. double-sided electrolytic plated board, 2: insulating board, 3: wiring pattern, 4: plated lead, 51-58: external terminal, 61-
68 Nisru ball, 7: IC chip setting section, 8.8a
: non-conductive pattern forming part, 9.9a: chamfering, ll:I
c card, 12: magnetic stripe, 13: hollow, 14:
IG chip. 15: Semiconductor device, 16: Bonding wire, 17:
Frame,) 8: Sealing resin Fig. 1]: Old: h + early glare angle, base 7 stone fork 51
~58, riL bottlep te 2) Speech color 1SX talent
6 Turn to the 3rd and D crossroads 8゛11゜7゜Lead on A1 and 4゛S. Fig. 7 21 Fig. 8 Fig. 9 Fig. 10 (a) 2a (b) 3'2a 3'l Standing a Fig. 10 (e) 3 Philo 36 Fig. 10 Fig. 11 Fig. 12 Fig. 24+ 41 214531 441 ! lrr
Claims (5)
第１パターン群が配列され、該第１パターン群を構成す
る全てのパターンに対応する裏面の位置にはそれぞれ第
２の同一パターンから成る第２パターン群が配列され、
これら第１及び第２パターン群を電解めっきで形成する
ためのリード線が上記第１パターン群の全てのパターン
と接続配線され、上記第１パターン群と第２パターン群
とはそれぞれ対応するパターン同士がスルーホール接続
されており、プレス打ち抜きで独立基板の多数個に分離
成形するためのプレス打ち抜き領域が各パターンに施さ
れている電解めっき基板を有する半導体装置において、
上記第２パターン群のそれぞれのパターンの全周辺部に
導電パターン非形成部を設けたことを特徴とする半導体
装置。(1) A plurality of first pattern groups consisting of the same pattern are arranged on the front surface of the insulating substrate, and second identical patterns are arranged at positions on the back surface corresponding to all the patterns constituting the first pattern group. The second pattern group is arranged,
Lead wires for forming these first and second pattern groups by electrolytic plating are connected to all the patterns in the first pattern group, and the first pattern group and the second pattern group are connected to corresponding patterns. In a semiconductor device having an electrolytically plated substrate, each pattern is provided with a press punching area for separating and molding a large number of independent substrates by press punching.
A semiconductor device characterized in that a conductive pattern-free portion is provided around the entire periphery of each pattern of the second pattern group.
、１ｍｍ以下の厚さを有する絶縁基板を用いたことを特
徴とする半導体装置。(2) A semiconductor device according to claim 1, characterized in that an insulating substrate having a thickness of 1 mm or less is used.
、導電パターン非形成領域の幅を０．１ｍｍ乃至０．６
ｍｍに形成したことを特徴とする半導体装置。(3) In the semiconductor device according to claim 1, the width of the conductive pattern-free region is 0.1 mm to 0.6 mm.
A semiconductor device characterized in that it is formed in mm.
第１の電解めっき導電パターンに導電パターンの非形成
領域を設け、第２の電解めっき導電パターンにめっきリ
ードを形成したことを特徴とする半導体装置。(4) In the semiconductor device according to claim 1,
A semiconductor device characterized in that a first electroplated conductive pattern is provided with a non-forming area of the conductive pattern, and a second electroplated conductive pattern is formed with a plated lead.
、めっきリードが形成されていない導電パターンと絶縁
基板の外周縁との間に、導電パターンの非形成領域を周
設したことを特徴とする半導体装置。(5) The semiconductor device according to claim 1, characterized in that a region where no conductive pattern is formed is provided between the conductive pattern where no plated lead is formed and the outer periphery of the insulating substrate. semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61113523A JPH07123182B2 (en) | 1986-05-20 | 1986-05-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61113523A JPH07123182B2 (en) | 1986-05-20 | 1986-05-20 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62271493A true JPS62271493A (en) | 1987-11-25 |
| JPH07123182B2 JPH07123182B2 (en) | 1995-12-25 |
Family
ID=14614499
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61113523A Expired - Lifetime JPH07123182B2 (en) | 1986-05-20 | 1986-05-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07123182B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63194773U (en) * | 1987-06-04 | 1988-12-15 | ||
| JP2007072066A (en) * | 2005-09-06 | 2007-03-22 | Sanyo Epson Imaging Devices Corp | Electrooptical apparatus, electronic equipment, and interface substrate |
| JP2009042777A (en) * | 2008-09-24 | 2009-02-26 | Epson Imaging Devices Corp | Electro-optical device and electronic apparatus |
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| JPS57188849A (en) * | 1981-04-30 | 1982-11-19 | Cii | Device for protecting electronic circuit against static charge |
| JPS5892597A (en) * | 1981-11-28 | 1983-06-01 | 大日本印刷株式会社 | Manufacture of identification card |
| JPS58118297A (en) * | 1981-12-31 | 1983-07-14 | 共同印刷株式会社 | Manufacture of identification card |
| JPS58155058U (en) * | 1982-04-09 | 1983-10-17 | 共同印刷株式会社 | memory card |
| JPS5948984A (en) * | 1982-09-13 | 1984-03-21 | 大日本印刷株式会社 | Method of producing ic card |
| JPS5957498A (en) * | 1982-09-28 | 1984-04-03 | 株式会社東芝 | Multilayer printed circuit board with through hole |
| JPS59132345A (en) * | 1983-01-19 | 1984-07-30 | Mitsubishi Electric Corp | Magnetic field generating device |
| JPS59173357U (en) * | 1983-05-06 | 1984-11-19 | 株式会社ニコン | Printed board |
| JPS6024093A (en) * | 1984-06-04 | 1985-02-06 | 株式会社日立製作所 | Method of producing ceramic circuit board |
| JPS6068488A (en) * | 1983-06-09 | 1985-04-19 | フロニク、ソシエテ、アノニム | Manufacture of memory card |
-
1986
- 1986-05-20 JP JP61113523A patent/JPH07123182B2/en not_active Expired - Lifetime
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5432137A (en) * | 1977-08-16 | 1979-03-09 | Tokyo Electric Co Ltd | Method of making pc plates |
| JPS5559795A (en) * | 1978-10-30 | 1980-05-06 | Nippon Electric Co | Printed circuit board and method of manufacturing same |
| JPS5750589A (en) * | 1980-09-09 | 1982-03-25 | Ebara Infilco Co Ltd | Desalting method for salt-containing water of high temperature |
| JPS57188849A (en) * | 1981-04-30 | 1982-11-19 | Cii | Device for protecting electronic circuit against static charge |
| JPS5892597A (en) * | 1981-11-28 | 1983-06-01 | 大日本印刷株式会社 | Manufacture of identification card |
| JPS58118297A (en) * | 1981-12-31 | 1983-07-14 | 共同印刷株式会社 | Manufacture of identification card |
| JPS58155058U (en) * | 1982-04-09 | 1983-10-17 | 共同印刷株式会社 | memory card |
| JPS5948984A (en) * | 1982-09-13 | 1984-03-21 | 大日本印刷株式会社 | Method of producing ic card |
| JPS5957498A (en) * | 1982-09-28 | 1984-04-03 | 株式会社東芝 | Multilayer printed circuit board with through hole |
| JPS59132345A (en) * | 1983-01-19 | 1984-07-30 | Mitsubishi Electric Corp | Magnetic field generating device |
| JPS59173357U (en) * | 1983-05-06 | 1984-11-19 | 株式会社ニコン | Printed board |
| JPS6068488A (en) * | 1983-06-09 | 1985-04-19 | フロニク、ソシエテ、アノニム | Manufacture of memory card |
| JPS6024093A (en) * | 1984-06-04 | 1985-02-06 | 株式会社日立製作所 | Method of producing ceramic circuit board |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63194773U (en) * | 1987-06-04 | 1988-12-15 | ||
| JP2007072066A (en) * | 2005-09-06 | 2007-03-22 | Sanyo Epson Imaging Devices Corp | Electrooptical apparatus, electronic equipment, and interface substrate |
| US7554643B2 (en) | 2005-09-06 | 2009-06-30 | Epson Imaging Devices Corporation | Electro-optical device, electronic apparatus, and interface board |
| JP2009042777A (en) * | 2008-09-24 | 2009-02-26 | Epson Imaging Devices Corp | Electro-optical device and electronic apparatus |
| JP4626694B2 (en) * | 2008-09-24 | 2011-02-09 | ソニー株式会社 | Electro-optical device and electronic apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07123182B2 (en) | 1995-12-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |