JPH04333267A - Manufacture of surface-mounting semiconductor device - Google Patents
Manufacture of surface-mounting semiconductor deviceInfo
- Publication number
- JPH04333267A JPH04333267A JP10232791A JP10232791A JPH04333267A JP H04333267 A JPH04333267 A JP H04333267A JP 10232791 A JP10232791 A JP 10232791A JP 10232791 A JP10232791 A JP 10232791A JP H04333267 A JPH04333267 A JP H04333267A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- groove
- plating layer
- resin
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000007747 plating Methods 0.000 claims abstract description 18
- 239000011347 resin Substances 0.000 claims abstract description 11
- 229920005989 resin Polymers 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 9
- 238000010008 shearing Methods 0.000 claims abstract description 5
- 238000007789 sealing Methods 0.000 claims description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 7
- 239000010931 gold Substances 0.000 abstract description 7
- 229910052737 gold Inorganic materials 0.000 abstract description 7
- 229910000679 solder Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910000531 Co alloy Inorganic materials 0.000 description 1
- KGWWEXORQXHJJQ-UHFFFAOYSA-N [Fe].[Co].[Ni] Chemical compound [Fe].[Co].[Ni] KGWWEXORQXHJJQ-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000007665 sagging Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は表面実装用の半導体装置
の製造方法に関して、特にリード切離し後のリード端面
の形状改善に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a surface-mounted semiconductor device, and more particularly to improving the shape of a lead end face after lead separation.
【０００２】0002
【従来の技術】従来の表面実装半導体装置の製造におい
ては、リード切離しを行なった後リード部のめっきを行
う方法がとられていた。すなわち、リードフレームに半
導体チップを搭載し、樹脂封止を行なった後、リード切
離しを行ない、リード部にめっき層を形成するのである
。2. Description of the Related Art In the conventional manufacturing of surface-mounted semiconductor devices, a method has been adopted in which the leads are separated and then the lead portions are plated. That is, after a semiconductor chip is mounted on a lead frame and resin-sealed, the leads are separated and a plating layer is formed on the lead portions.
【０００３】0003
【発明が解決しようとする課題】この従来の表面実装半
導体装置の製造方法においては、リードが切離された状
態でめっきが行なわれるためにめっき工程中のハンドリ
ング等により、リードが曲る場合があり、後の工程でリ
ード修正を行なう必要があるという問題点がある。さら
にリード厚さが０．２ｍｍ以下の非常に薄いリードにな
ると、リード曲りが非常に発生しやすくなるため、リー
ド切離しを行う前にめっきを行なう必要がある。しかし
ながら、この場合にはリードの端面すなわち切断した面
にめっきがされていないため、実装時にリード端面への
半田付着性が悪くなる場合がある。図５にめっきをした
後切離しを行なった場合のリード端面形状を示す。リー
ド端面の上側はリード表面のめっき層がだれており、め
っき金属が表面に付着しているのに対してリード端面の
下側（破断面１０）にはめっき金属は付着しない。従っ
て実装した場合半田の付着性が悪いという問題がある。
図６，図７に示すように、このような半導体装置をプリ
ント基板１０３に実装した場合のリード端面に半田フィ
レット１０４ａが付着しない場合がある。[Problems to be Solved by the Invention] In this conventional method for manufacturing surface-mounted semiconductor devices, since plating is performed with the leads separated, the leads may be bent due to handling during the plating process. However, there is a problem in that it is necessary to correct the lead in a later process. Furthermore, when the lead is very thin, with a lead thickness of 0.2 mm or less, lead bending is very likely to occur, so it is necessary to perform plating before cutting the lead. However, in this case, since the end faces of the leads, that is, the cut faces are not plated, the solder adhesion to the lead end faces may be poor during mounting. FIG. 5 shows the shape of the lead end face when the lead is separated after plating. The plating layer on the lead surface is sagging on the upper side of the lead end face, and the plated metal adheres to the surface, whereas no plated metal adheres to the lower side of the lead end face (fracture surface 10). Therefore, when mounted, there is a problem of poor solder adhesion. As shown in FIGS. 6 and 7, when such a semiconductor device is mounted on a printed circuit board 103, the solder fillet 104a may not adhere to the lead end face.
【０００４】0004
【課題を解決するための手段】本発明の表面実装半導体
装置の製造方法は、リードの所定箇所に所定寸法の溝を
設けたリードフレームを準備する工程と、前記リードフ
レームに半導体チップを搭載し樹脂封止する工程と、前
記リードフレームの封止樹脂で覆われていないリード表
面にめっき層を形成する工程と、前記リードの溝のある
表面をダイで受けてせん断加工によりリードを外枠から
切離す工程とを有するというものである。[Means for Solving the Problems] A method for manufacturing a surface-mounted semiconductor device according to the present invention includes the steps of preparing a lead frame in which grooves of a predetermined size are provided at predetermined positions of leads, and mounting a semiconductor chip on the lead frame. A step of resin sealing, a step of forming a plating layer on the lead surface not covered with the sealing resin of the lead frame, and a step of receiving the grooved surface of the lead with a die and shearing the lead from the outer frame. The method includes a step of separating.
【０００５】[0005]
【実施例】図１〜図３を参照して本発明の一実施例につ
いて説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. 1 to 3.
【０００６】本実施例は、図１に示すように、リード２
の所定箇所に所定寸法の溝３を設けたリードフレームを
準備する工程と、前述のリードフレームに図示しない半
導体チップを搭載し樹脂封止する工程と、図２に示すよ
うに、前述のリードフレームの封止樹脂１で覆われてい
ないリード２表面にめっき層６を形成する工程と、リー
ドの溝３のある表面をダイ８で受けてせん断加工により
リードを外枠５から切離す工程とを有するというもので
ある。図３に示すように、溝部分にはもともとめっき層
６が形成されているが、切断面の部分にも、リード表面
のめっき層がだれており、端面全部に金が付着した状態
となる。In this embodiment, as shown in FIG.
A step of preparing a lead frame having a groove 3 of a predetermined size in a predetermined location of the lead frame, a step of mounting a semiconductor chip (not shown) on the lead frame and sealing it with resin, and as shown in FIG. a step of forming a plating layer 6 on the surface of the lead 2 that is not covered with the sealing resin 1; and a step of receiving the surface of the lead with the groove 3 with a die 8 and separating the lead from the outer frame 5 by shearing. It means having. As shown in FIG. 3, a plating layer 6 was originally formed in the groove portion, but the plating layer on the lead surface also sagged at the cut surface, resulting in gold adhering to the entire end surface.
【０００７】リードフレームの材質は厚さ０．１２５ｍ
ｍの鉄−ニッケル−コバルト合金板を使用し、厚さ１０
μｍの金めっきを行なうものとする。溝３の幅は１００
μｍ、深さは６５μｍである。実験によると、溝３の深
さをリード２の厚さの少なくとも１／２とすることによ
り、厚さ０．１５μｍ以下のリードの場合、標準的なせ
ん断加工により端面のほぼ全面に金を付着させることが
できた。[0007] The material of the lead frame is 0.125 m thick.
10m iron-nickel-cobalt alloy plate with a thickness of 10m.
It is assumed that μm gold plating is performed. The width of groove 3 is 100
μm, and the depth is 65 μm. Experiments have shown that by setting the depth of groove 3 to at least 1/2 of the thickness of lead 2, gold can be deposited on almost the entire end face using standard shearing for leads with a thickness of 0.15 μm or less. I was able to do it.
【０００８】本実施例の表面実装半導体装置を実装する
と、図４に示すように、半田フィレット１０４がリード
１０２の端面に十分に接合される。リード端面の半田付
着性が改善されるからである。When the surface-mounted semiconductor device of this embodiment is mounted, the solder fillet 104 is sufficiently bonded to the end surface of the lead 102, as shown in FIG. This is because the solder adhesion of the lead end face is improved.
【０００９】[0009]
【発明の効果】以上説明したように本発明によれば、リ
ード切離し工程の前にリードにめっきを行なうので、め
っき工程におけるハンドリングによるリード曲りの発生
がない、リード端面の全部分にめっき金属を付着させる
ことができ、実装した時にリード端面の半田付着性が従
来より改善されるという効果がある。As explained above, according to the present invention, since the leads are plated before the lead separation process, there is no bending of the leads due to handling in the plating process, and the entire lead end face is covered with plated metal. This has the effect that the solder adhesion on the lead end face is improved compared to the conventional method when mounted.
【図１】本発明の一実施例の説明に使用する平面図であ
る。FIG. 1 is a plan view used to explain one embodiment of the present invention.
【図２】本発明の一実施例の説明に使用する断面図であ
る。FIG. 2 is a sectional view used to explain one embodiment of the present invention.
【図３】本発明の一実施例の説明に使用する断面図であ
る。FIG. 3 is a sectional view used to explain one embodiment of the present invention.
【図４】本発明の一実施例による表面実装半導体装置の
実装状態を示す断面図である。FIG. 4 is a cross-sectional view showing a mounted state of a surface-mounted semiconductor device according to an embodiment of the present invention.
【図５】従来の技術の説明に使用する断面図である。FIG. 5 is a cross-sectional view used to explain the conventional technology.
【図６】表面実装半導体装置の実装状態を示す断面図で
ある。FIG. 6 is a cross-sectional view showing a mounted state of a surface-mounted semiconductor device.
【図７】従来の技術の説明に使用する断面図である。FIG. 7 is a cross-sectional view used to explain the conventional technology.
１ 封止樹脂
２ リード
３ 溝
４ 吊りピン
５ 外枠
６ めっき層
７ パンチ
８ ダイ
９ 切断面
１０ 破断面
１０１ 表面実装半導体装置
１０２ リード
１０３ プリント基板
１０４，１０４ａ 半田フィレット１０５
プリント基板の電極1 Sealing resin 2 Lead 3 Groove 4 Hanging pin 5 Outer frame 6 Plating layer 7 Punch 8 Die 9 Cut surface 10 Fracture surface 101 Surface mount semiconductor device 102 Lead 103 Printed circuit board 104, 104a Solder fillet 105
printed circuit board electrode
Claims (2)
リードフレームを準備する工程と、前記リードフレーム
に半導体チップを搭載し樹脂封止する工程と、前記リー
ドフレームの封止樹脂で覆われていないリード表面にめ
っき層を形成する工程と、前記リードの溝のある表面を
ダイで受けてせん断加工によりリードを外枠から切離す
工程とを有することを特徴とする表面実装半導体装置の
製造方法。1. A step of preparing a lead frame in which a groove of a predetermined size is provided at a predetermined location of a lead, a step of mounting a semiconductor chip on the lead frame and sealing it with a resin, and covering the lead frame with a sealing resin. A surface mount semiconductor device comprising the steps of: forming a plating layer on the surface of the lead which is not covered; and receiving the grooved surface of the lead with a die and separating the lead from the outer frame by shearing. Production method.
２である請求項１記載の表面実装半導体装置の製造方法
。2. The depth of the groove is at least 1/of the thickness of the lead.
2. The method for manufacturing a surface-mounted semiconductor device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10232791A JPH04333267A (en) | 1991-05-08 | 1991-05-08 | Manufacture of surface-mounting semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10232791A JPH04333267A (en) | 1991-05-08 | 1991-05-08 | Manufacture of surface-mounting semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04333267A true JPH04333267A (en) | 1992-11-20 |
Family
ID=14324449
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10232791A Pending JPH04333267A (en) | 1991-05-08 | 1991-05-08 | Manufacture of surface-mounting semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04333267A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008034830A (en) * | 2006-06-27 | 2008-02-14 | Seiko Instruments Inc | Semiconductor device, and lead frame and its manufacturing method |
| JP2013118270A (en) * | 2011-12-02 | 2013-06-13 | Renesas Electronics Corp | Method of manufacturing semiconductor device, and semiconductor device |
| JP2015072947A (en) * | 2013-10-01 | 2015-04-16 | セイコーインスツル株式会社 | Semiconductor device and manufacturing method of the same |
-
1991
- 1991-05-08 JP JP10232791A patent/JPH04333267A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008034830A (en) * | 2006-06-27 | 2008-02-14 | Seiko Instruments Inc | Semiconductor device, and lead frame and its manufacturing method |
| JP2013118270A (en) * | 2011-12-02 | 2013-06-13 | Renesas Electronics Corp | Method of manufacturing semiconductor device, and semiconductor device |
| JP2015072947A (en) * | 2013-10-01 | 2015-04-16 | セイコーインスツル株式会社 | Semiconductor device and manufacturing method of the same |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19990330 |