JP2008034830A - Semiconductor device, and lead frame and its manufacturing method - Google Patents

Semiconductor device, and lead frame and its manufacturing method Download PDF

Info

Publication number
JP2008034830A
JP2008034830A JP2007168472A JP2007168472A JP2008034830A JP 2008034830 A JP2008034830 A JP 2008034830A JP 2007168472 A JP2007168472 A JP 2007168472A JP 2007168472 A JP2007168472 A JP 2007168472A JP 2008034830 A JP2008034830 A JP 2008034830A
Authority
JP
Japan
Prior art keywords
terminal
semiconductor device
lead frame
resin mold
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2007168472A
Other languages
Japanese (ja)
Inventor
Tomoyuki Yoshino
朋之 吉野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP2007168472A priority Critical patent/JP2008034830A/en
Publication of JP2008034830A publication Critical patent/JP2008034830A/en
Priority to US12/215,168 priority patent/US7786556B2/en
Priority to TW097123934A priority patent/TWI492352B/en
Priority to KR20080061422A priority patent/KR101494011B1/en
Priority to CN2008101285366A priority patent/CN101335251B/en
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To prevent bonding strength deterioration owing to poor solder wettability of a terminal when a semiconductor device is mounted on a circuit board or the like. <P>SOLUTION: A semiconductor device bonding strength with the circuit board of which is improved owing to improvement of the solder wettability of its terminal achieved by covering all or at least half of a cross-sectional area of an end portion of the terminal of the semiconductor device with a plated layer, is disclosed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、リードフレームに搭載された半導体集積回路等の素子を樹脂モールドして成る半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device formed by resin molding an element such as a semiconductor integrated circuit mounted on a lead frame, and a method for manufacturing the same.

リードフレームに搭載された半導体集積回路等の素子を樹脂モールドした半導体装置は通常回路基板に実装されて使用される。そこで半導体装置と回路基板の十分な実装強度を確保するために半導体装置の端子を長くすることで接合面積を大きくしていた。従来から半導体装置の端子切断面のハンダ濡れ性は良い状態では無かったが、接合面積が大きく、端子の形状自体もZ字型にフォーミングしているため、端子の両端だけでなく、端子かかと部のハンダ濡れ性が良好であったため、ハンダが端子を這い上がり、その結果十分な実装強度の確保が出来ていた。
特開平10−223822号公報
A semiconductor device in which an element such as a semiconductor integrated circuit mounted on a lead frame is resin-molded is usually mounted on a circuit board and used. Therefore, in order to secure sufficient mounting strength between the semiconductor device and the circuit board, the junction area is increased by lengthening the terminals of the semiconductor device. Conventionally, solder wettability of the terminal cut surface of the semiconductor device has not been in a good state, but since the bonding area is large and the terminal shape itself is formed in a Z shape, not only both ends of the terminal but also the terminal heel part Since the solder wettability of the solder was good, the solder scooped up the terminals, and as a result, sufficient mounting strength was secured.
JP-A-10-223822

接合面積が大きければ、実装強度も確保できるが、半導体装置の小型化が進むにしたがい、回路基板への実装強度は低下する傾向にある。実装密度を上げるためには回路基板と接合する半導体装置の端子面積及び回路基板側の電極面積を小さくする必要があるからである。半導体装置を回路基板に実装する時には主にハンダが用いられるが、半導体装置の端子がハンダに対して濡れやすいか否かで実装強度が大きく変わってくる。ハンダはリフローなどで溶融温度に達すると、半導体装置の端子のメッキと共に溶融していく。その時に半導体装置の端子全体にメッキが形成されているのが望ましく、メッキが存在しない部分はハンダによって濡れることは無いため、その部分だけ強度が弱くなってしまう。小型の半導体装置になるほど、半導体装置の端子と回路基板の電極間のハンダによる接合だけでは十分な強度は得られないことになってしまうため、少しでも多く、ハンダが濡れる面積を確保する必要がある。特に半導体装置の端子先端部のハンダ濡れ性は重要である。これは、半導体装置が回路基板に実装された場合、端子先端部が回路基板の反りなどの影響を受けやすいためである。   If the bonding area is large, the mounting strength can be ensured, but the mounting strength on the circuit board tends to decrease as the semiconductor device is miniaturized. This is because in order to increase the mounting density, it is necessary to reduce the terminal area of the semiconductor device to be bonded to the circuit board and the electrode area on the circuit board side. Solder is mainly used when a semiconductor device is mounted on a circuit board, but the mounting strength varies greatly depending on whether or not the terminals of the semiconductor device are easily wetted with the solder. When the solder reaches the melting temperature by reflow or the like, it melts together with the plating of the terminals of the semiconductor device. At that time, it is desirable that plating is formed on the entire terminal of the semiconductor device, and a portion where the plating is not present is not wetted by the solder, so that only that portion is weakened. As the size of the semiconductor device becomes smaller, sufficient strength cannot be obtained simply by bonding between the terminals of the semiconductor device and the electrodes of the circuit board, so it is necessary to secure an area where the solder gets wet as much as possible. is there. In particular, the solder wettability of the tip of the terminal of the semiconductor device is important. This is because when the semiconductor device is mounted on the circuit board, the terminal tip is easily affected by the warp of the circuit board.

図6は従来の半導体装置の構造を示す模式側面図を示している。従来は図6に示したように、樹脂1から端子2が突出し、フォーミングされている。端子2はメッキ層3で覆われているが、端子先端切断部10には端子2の切断によって、端子先端露出部12が形成されている。この端子先端露出部12が存在することで、回路基板などへ実装するときに接合剤となるハンダ材の濡れ性が悪くなってしまう。   FIG. 6 is a schematic side view showing the structure of a conventional semiconductor device. Conventionally, as shown in FIG. 6, the terminal 2 protrudes from the resin 1 and is formed. Although the terminal 2 is covered with the plating layer 3, a terminal tip exposed portion 12 is formed in the terminal tip cutting portion 10 by cutting the terminal 2. The presence of the terminal tip exposed portion 12 deteriorates the wettability of the solder material used as a bonding agent when mounted on a circuit board or the like.

図7は製造工程途中の従来の半導体装置の構造図を示している。図7の様に二つの樹脂21と樹脂31を結ぶリードフレームの一部でもある端子2は太さが一様である。このような構造の半導体装置を切断して個片化すると、図6に示したような端子露出部12が形成されてしまう。   FIG. 7 shows a structural diagram of a conventional semiconductor device in the middle of a manufacturing process. As shown in FIG. 7, the terminal 2 which is also a part of the lead frame connecting the two resins 21 and 31 has a uniform thickness. When the semiconductor device having such a structure is cut into pieces, the terminal exposed portion 12 as shown in FIG. 6 is formed.

半導体装置の端子と回路基板の電極を強固に接合するために、半導体装置の端子のハンダ濡れ性を向上させる手段として半導体装置の端子先端部の全体にメッキが形成された半導体装置とした。また、他の手段として、半導体装置の端子先端部の切断面においてメッキが形成されない面積は端子の断面積の二分の一以下である半導体装置とした。   In order to firmly bond the terminal of the semiconductor device and the electrode of the circuit board, a semiconductor device in which plating is formed on the entire terminal tip portion of the semiconductor device as a means for improving solder wettability of the terminal of the semiconductor device. As another means, a semiconductor device in which the area where the plating is not formed on the cut surface of the terminal tip of the semiconductor device is one half or less of the cross-sectional area of the terminal.

本発明によれば、半導体装置の端子面積を大きくすることなく、ハンダ材がリフロー時の熱で溶融し、端子上面まで這い上がり、回路基板との実装強度を向上することが可能となる。また実装した回路基板の反りなどに対する強度も向上させることが出来る。   According to the present invention, without increasing the terminal area of the semiconductor device, the solder material is melted by the heat during reflow and crawls up to the upper surface of the terminal, so that the mounting strength with the circuit board can be improved. Further, the strength against the warp of the mounted circuit board can be improved.

以下、本発明の半導体装置の実施例について図面に基づいて説明する。   Embodiments of a semiconductor device according to the present invention will be described below with reference to the drawings.

図1は本発明の第1の実施例である半導体装置の構造を示す模式側面図である。半導体装置は樹脂1、端子2、及び端子表面を被覆する金属メッキ3からなる。半導体集積回路(ICチップ)等の素子は樹脂1に覆われており、通常外部からは見えない構成となっている。端子2の一端は樹脂1内部で半導体集積回路と電気的に接合され、他端は樹脂1から突出した形態を示しており、端子の突出部は金型などによって基板への実装に適した形にフォーミングされている。端子2が樹脂1の外部に露出している部分の表面にはほぼ全体にわたりメッキ層3が形成されている。図1に示した実施例では、端子2の端部においてもメッキ層3がその端子先端部4を覆っており、端子2の表面は外部に露出することがない。   FIG. 1 is a schematic side view showing the structure of a semiconductor device according to a first embodiment of the present invention. The semiconductor device includes a resin 1, a terminal 2, and a metal plating 3 that covers the surface of the terminal. An element such as a semiconductor integrated circuit (IC chip) is covered with a resin 1 and is normally invisible from the outside. One end of the terminal 2 is electrically joined to the semiconductor integrated circuit inside the resin 1, and the other end protrudes from the resin 1, and the protruding portion of the terminal has a shape suitable for mounting on a substrate by a mold or the like. Has been formed. A plating layer 3 is formed almost entirely on the surface of the portion where the terminal 2 is exposed to the outside of the resin 1. In the embodiment shown in FIG. 1, the plating layer 3 covers the terminal tip 4 at the end of the terminal 2 and the surface of the terminal 2 is not exposed to the outside.

図2は本発明の第2の実施例である半導体装置の構造を示す模式側面図である。本図に示した実施例においては、端子2の端子先端部4にはメッキ層3に覆われている部分とメッキ層3に覆われていない端子先端露出部5とが存在する。端子先端露出部5の断面積を端子2の断面積の二分の一以下にすることで、半導体装置を回路基板などへ実装するときにその接合部材となるハンダ材がメッキ層を濡らしやすくなり、端子先端部4をハンダが這い上がり、強固な実装状態を形成することが出来るようになる。   FIG. 2 is a schematic side view showing the structure of the semiconductor device according to the second embodiment of the present invention. In the embodiment shown in this figure, the terminal tip 4 of the terminal 2 has a portion covered with the plating layer 3 and a terminal tip exposed portion 5 not covered with the plating layer 3. By making the cross-sectional area of the terminal tip exposed portion 5 less than or equal to one-half of the cross-sectional area of the terminal 2, the solder material that becomes a joining member when the semiconductor device is mounted on a circuit board or the like can easily wet the plating layer, Solder crawls up the terminal tip 4 so that a strong mounting state can be formed.

図3は本発明に係るリードフレームの第1の実施例を示している。一枚のリードフレーム上に半導体装置を複数配置した集合体を示している。各半導体装置の端子8はメッキバー7で繋がっており、メッキバー7は端子8の側面で接合している。メッキバー7はリードフレーム6に電解メッキを行うときに電気を流すための通路である。このようにメッキバー7が端子8の側面で接合する構造にすることで、図1に示した様に端子先端部4をメッキ層3で覆った構造の半導体装置を製造することが可能になる。   FIG. 3 shows a first embodiment of the lead frame according to the present invention. An assembly in which a plurality of semiconductor devices are arranged on one lead frame is shown. The terminals 8 of each semiconductor device are connected by a plating bar 7, and the plating bar 7 is joined at the side surface of the terminal 8. The plating bar 7 is a passage through which electricity flows when electrolytic plating is performed on the lead frame 6. As described above, the structure in which the plating bar 7 is joined to the side surface of the terminal 8 makes it possible to manufacture a semiconductor device having a structure in which the terminal tip 4 is covered with the plating layer 3 as shown in FIG.

図4は本発明に係るリードフレームの第2の実施例を示している。一枚のリードフレーム上に半導体装置を複数配置した集合体を示している。ここでは、各半導体装置の端子8を延長してメッキバー9を形成している。メッキバー9はリードフレーム6に電解メッキを行うときに電気を流すための通路である。メッキバー9が端子8に接合している部分は、後から切断するときの切断面となり、メッキが付かないため、メッキバー9の断面積は端子8の断面積の2分の1未満で、出来るだけ細く、薄いことが望ましい。   FIG. 4 shows a second embodiment of the lead frame according to the present invention. An assembly in which a plurality of semiconductor devices are arranged on one lead frame is shown. Here, the plating bar 9 is formed by extending the terminal 8 of each semiconductor device. The plating bar 9 is a passage through which electricity flows when electrolytic plating is performed on the lead frame 6. The portion where the plating bar 9 is joined to the terminal 8 becomes a cut surface when it is cut later, and plating is not applied. Thin and thin are desirable.

図5は本発明の第2の実施例である半導体装置の側面図であり、製造の途中の状態を示している。隣り合う二つの半導体装置がリードフレームで接続された状態を示している。図5に示すように本発明ではリードフレーム2にリードフレーム薄部11を形成した。リードフレーム薄部11を切断して半導体装置を個片化することで、図2に示した実施例の構造を有する半導体装置を得ることが出来る。   FIG. 5 is a side view of a semiconductor device according to a second embodiment of the present invention, and shows a state in the middle of manufacture. 2 shows a state in which two adjacent semiconductor devices are connected by a lead frame. As shown in FIG. 5, in the present invention, the lead frame thin portion 11 is formed on the lead frame 2. The semiconductor device having the structure of the embodiment shown in FIG. 2 can be obtained by cutting the lead frame thin portion 11 to separate the semiconductor device.

図8は本発明の第3の実施例である半導体装置の製造途中を示す側面図であり、隣り合う二つの半導体装置がリードフレームで接続された状態を示している。図8に示すように本実施例においてはリードフレーム2にリードフレーム薄部11を形成する。リードフレーム薄部11は半導体装置を回路基板に実装する面側に形成されている。リードフレーム薄部11を切断して半導体装置を個片化することで、図9に示される構造を有する第3の実施例である半導体装置を得ることが出来る。この様な構造とすることで回路基板に印刷された半田がリード上面を濡らしやすくなる。   FIG. 8 is a side view showing the process of manufacturing a semiconductor device according to the third embodiment of the present invention, and shows a state in which two adjacent semiconductor devices are connected by a lead frame. As shown in FIG. 8, in this embodiment, the lead frame thin portion 11 is formed on the lead frame 2. The lead frame thin portion 11 is formed on the surface side on which the semiconductor device is mounted on the circuit board. By cutting the lead frame thin portion 11 and dividing the semiconductor device into pieces, the semiconductor device according to the third embodiment having the structure shown in FIG. 9 can be obtained. With such a structure, the solder printed on the circuit board easily wets the upper surface of the lead.

リードフレーム薄部11の形成方法は、最初にプレス金型でリードフレームの所望の形状に抜いた後で部分的に加工する。その部分的な加工方法としては、薬品によってエッチングして肉薄部を形成する方法とプレス加工によって局所的な潰し加工を行う方法などがある。   The lead frame thin part 11 is formed by first processing the lead frame with a press die after extracting the lead frame into a desired shape. As the partial processing method, there are a method of forming a thin portion by etching with a chemical, a method of performing a local crushing process by pressing, and the like.

最後に製造工程を概略説明する。リードフレーム上に半導体集積回路(ICチップ)を接着し、半導体集積回路とリードフレームをワイヤーで接続する。その後樹脂で半導体集積回路を覆う。ここまでの工程で図3および図4の状態になる。その後メッキ処理を行うと樹脂以外の部分は全体的にメッキ皮膜で覆われる。更に金型などでリードフレームを切断して半導体装置を個片化する。   Finally, the manufacturing process will be outlined. A semiconductor integrated circuit (IC chip) is bonded on the lead frame, and the semiconductor integrated circuit and the lead frame are connected by a wire. Thereafter, the semiconductor integrated circuit is covered with resin. The state up to here is the state shown in FIGS. Thereafter, when plating is performed, portions other than the resin are entirely covered with a plating film. Further, the lead frame is cut with a mold or the like to separate the semiconductor device.

本発明による半導体装置は、携帯電話、ノートパソコン、携帯電子機器などの小型で軽量であることを要求される製品に幅広く利用できる。   The semiconductor device according to the present invention can be widely used for products that are required to be small and light, such as mobile phones, notebook computers, and portable electronic devices.

本発明による半導体装置の第1の実施例を示す模式側面図である。1 is a schematic side view showing a first embodiment of a semiconductor device according to the present invention. 本発明による半導体装置の第2の実施例を示す模式側面図である。It is a schematic side view which shows the 2nd Example of the semiconductor device by this invention. 本発明によるリードフレームの第1の実施例を示す模式平面図である。1 is a schematic plan view showing a first embodiment of a lead frame according to the present invention. 本発明によるリードフレームの第2の実施例を示す模式平面図である。FIG. 6 is a schematic plan view showing a second embodiment of the lead frame according to the present invention. 本発明によるリードフレームを部分的に表した模式側面図である。It is the model side view which represented the lead frame by this invention partially. 従来の半導体装置の構造を示す模式側面図である。It is a model side view which shows the structure of the conventional semiconductor device. 従来のリードフレームを部分的に表した模式側面図である。It is the model side view which represented the conventional lead frame partially. 本発明による半導体装置の実施例を示す模式側面図である。It is a schematic side view which shows the Example of the semiconductor device by this invention. 本発明による半導体装置の実施例を示す模式側面図である。It is a schematic side view which shows the Example of the semiconductor device by this invention.

符号の説明Explanation of symbols

1 樹脂
2 端子
3 メッキ層
4 端子先端部
5 端子先端露出部
6 リードフレーム
7 メッキバー
8 端子
9 メッキバー
10 端子先端切断部
11 リードフレーム薄部
12 端子先端露出部
21 樹脂
31 樹脂
DESCRIPTION OF SYMBOLS 1 Resin 2 Terminal 3 Plating layer 4 Terminal tip part 5 Terminal tip exposed part 6 Lead frame 7 Plating bar 8 Terminal 9 Plating bar 10 Terminal tip cutting part 11 Lead frame thin part 12 Terminal tip exposed part 21 Resin 31 Resin

Claims (7)

樹脂モールドで覆われた素子と、前記樹脂モールドから突出した金属製の端子を有する半導体装置であって、前記端子の先端部は端面の全面が半田メッキで覆われている半導体装置   A semiconductor device having an element covered with a resin mold and a metal terminal protruding from the resin mold, wherein the end portion of the terminal is entirely covered with solder plating. 樹脂モールドで覆われた素子と、前記樹脂モールドから突出した金属製の端子を有する半導体装置であって、前記端子の先端部の半田メッキで覆われていない部分の面積は前期端面の断面積の二分の一以下である半導体装置   A semiconductor device having an element covered with a resin mold and a metal terminal protruding from the resin mold, the area of the portion not covered with solder plating at the tip of the terminal is the cross-sectional area of the end face Semiconductor device that is less than half 樹脂モールドで覆われた素子と、前記樹脂モールドから突出した金属製の端子を有する半導体装置の製造に用いられるリードフレームであって、前記端子の前記樹脂モールドにより覆われていない部分の側面に配置されたメッキバーによりリードフレームに接続されているリードフレーム。   A lead frame used for manufacturing a semiconductor device having an element covered with a resin mold and a metal terminal protruding from the resin mold, and disposed on a side surface of a portion of the terminal not covered by the resin mold The lead frame is connected to the lead frame by the plated bar. 樹脂モールドで覆われた素子と、前記樹脂モールドから突出した金属製の端子を有する半導体装置の製造に用いられるリードフレームであって、前記端子の前記樹脂モールドにより覆われていない部分の端子先端面は、その断面積が前記端子の断面積の2分の1未満であるメッキバーによりリードフレームに接続されているリードフレーム。   A lead frame used for manufacturing a semiconductor device having an element covered with a resin mold and a metal terminal protruding from the resin mold, and a terminal front end surface of a portion of the terminal not covered with the resin mold Is a lead frame connected to the lead frame by a plating bar whose cross-sectional area is less than half of the cross-sectional area of the terminal. 樹脂モールドで覆われた素子と、前記樹脂モールドから突出した金属製の端子を有する半導体装置の製造に用いられるリードフレームであって、前記端子の前記樹脂モールドにより覆われていない部分の端子先端面は、半導体装置を回路基板に実装する面側から前記端子の厚みの2分の1未満であるメッキバーによりリードフレームに接続されているリードフレーム。   A lead frame used for manufacturing a semiconductor device having an element covered with a resin mold and a metal terminal protruding from the resin mold, and a terminal front end surface of a portion of the terminal not covered with the resin mold Is a lead frame connected to the lead frame by a plating bar that is less than one-half of the thickness of the terminal from the surface side on which the semiconductor device is mounted on the circuit board. 樹脂モールドで覆われた素子と、前記樹脂モールドから突出した金属製の端子を有する半導体装置の製造に用いられるリードフレームの製造方法において、プレス加工により半導体チップを搭載する部分、回路基板と接続する端子、及び端子部にメッキ処理を行うためのメッキバーを形成する工程と、前記メッキバーの一部を薬品でエッチング処理して薄くする工程とからなることを特徴とするリードフレームの製造方法。   In a manufacturing method of a lead frame used for manufacturing a semiconductor device having an element covered with a resin mold and a metal terminal protruding from the resin mold, a portion on which a semiconductor chip is mounted by press working and connected to a circuit board A method of manufacturing a lead frame, comprising: forming a terminal and a plating bar for plating on the terminal portion; and etching the part of the plating bar with a chemical to make it thin. 樹脂モールドで覆われた素子と、前記樹脂モールドから突出した金属製の端子を有する半導体装置の製造に用いられるリードフレームの製造方法において、プレス加工により半導体チップを搭載する部分、回路基板と接続する端子、及び端子部にメッキ処理を行うためのメッキバーを形成する工程と、前記メッキバーの一部を再度プレス処理して薄くする工程とからなることを特徴とするリードフレームの製造方法。   In a manufacturing method of a lead frame used for manufacturing a semiconductor device having an element covered with a resin mold and a metal terminal protruding from the resin mold, a portion on which a semiconductor chip is mounted by press working and connected to a circuit board A method of manufacturing a lead frame, comprising: forming a terminal and a plating bar for performing plating on the terminal portion; and pressing the part of the plating bar again to make it thin.
JP2007168472A 2006-06-27 2007-06-27 Semiconductor device, and lead frame and its manufacturing method Withdrawn JP2008034830A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2007168472A JP2008034830A (en) 2006-06-27 2007-06-27 Semiconductor device, and lead frame and its manufacturing method
US12/215,168 US7786556B2 (en) 2007-06-27 2008-06-25 Semiconductor device and lead frame used to manufacture semiconductor device
TW097123934A TWI492352B (en) 2007-06-27 2008-06-26 Semiconductor device, lead frame, and manufacturing method for the lead frame
KR20080061422A KR101494011B1 (en) 2007-06-27 2008-06-27 Semiconductor device, lead frame, and manufacturing method for the lead frame
CN2008101285366A CN101335251B (en) 2007-06-27 2008-06-27 Semiconductor device, lead frame, and manufacturing method for the lead frame

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006176108 2006-06-27
JP2007168472A JP2008034830A (en) 2006-06-27 2007-06-27 Semiconductor device, and lead frame and its manufacturing method

Publications (1)

Publication Number Publication Date
JP2008034830A true JP2008034830A (en) 2008-02-14

Family

ID=39123888

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007168472A Withdrawn JP2008034830A (en) 2006-06-27 2007-06-27 Semiconductor device, and lead frame and its manufacturing method

Country Status (1)

Country Link
JP (1) JP2008034830A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012231068A (en) * 2011-04-27 2012-11-22 Nichia Chem Ind Ltd Light emitting device
JP2016167532A (en) * 2015-03-10 2016-09-15 新日本無線株式会社 Lead frame and manufacturing method of semiconductor device using the same

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02302068A (en) * 1989-05-16 1990-12-14 Nec Corp Transfer mold type hybrid integrated circuit
JPH04162466A (en) * 1990-10-24 1992-06-05 Nec Corp Lead frame for semiconductor device
JPH04171855A (en) * 1990-11-05 1992-06-19 Nec Kyushu Ltd Lead frame for semiconductor device
JPH04326755A (en) * 1991-04-26 1992-11-16 Matsushita Electron Corp Resin-sealed semiconductor device and manufacture thereof
JPH04333267A (en) * 1991-05-08 1992-11-20 Nec Corp Manufacture of surface-mounting semiconductor device
JPH04368157A (en) * 1991-06-17 1992-12-21 Nec Corp Surface mounting type semiconductor device and manufacture thereof
JPH05291456A (en) * 1992-04-15 1993-11-05 Yamaha Corp Lead frame and processing method therefor
JPH05326788A (en) * 1992-05-25 1993-12-10 Nippon Steel Corp Lead frame material and semiconductor device provided therewith
JPH07211838A (en) * 1994-01-12 1995-08-11 Sony Corp Lead cut equipment of semiconductor device
JPH0864743A (en) * 1994-08-24 1996-03-08 Sony Corp Lead frame and manufacture of semiconductor device using the lead frame
JPH10313082A (en) * 1997-03-10 1998-11-24 Sanyo Electric Co Ltd Semiconductor device and manufacture thereof

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02302068A (en) * 1989-05-16 1990-12-14 Nec Corp Transfer mold type hybrid integrated circuit
JPH04162466A (en) * 1990-10-24 1992-06-05 Nec Corp Lead frame for semiconductor device
JPH04171855A (en) * 1990-11-05 1992-06-19 Nec Kyushu Ltd Lead frame for semiconductor device
JPH04326755A (en) * 1991-04-26 1992-11-16 Matsushita Electron Corp Resin-sealed semiconductor device and manufacture thereof
JPH04333267A (en) * 1991-05-08 1992-11-20 Nec Corp Manufacture of surface-mounting semiconductor device
JPH04368157A (en) * 1991-06-17 1992-12-21 Nec Corp Surface mounting type semiconductor device and manufacture thereof
JPH05291456A (en) * 1992-04-15 1993-11-05 Yamaha Corp Lead frame and processing method therefor
JPH05326788A (en) * 1992-05-25 1993-12-10 Nippon Steel Corp Lead frame material and semiconductor device provided therewith
JPH07211838A (en) * 1994-01-12 1995-08-11 Sony Corp Lead cut equipment of semiconductor device
JPH0864743A (en) * 1994-08-24 1996-03-08 Sony Corp Lead frame and manufacture of semiconductor device using the lead frame
JPH10313082A (en) * 1997-03-10 1998-11-24 Sanyo Electric Co Ltd Semiconductor device and manufacture thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012231068A (en) * 2011-04-27 2012-11-22 Nichia Chem Ind Ltd Light emitting device
JP2016167532A (en) * 2015-03-10 2016-09-15 新日本無線株式会社 Lead frame and manufacturing method of semiconductor device using the same

Similar Documents

Publication Publication Date Title
US7786556B2 (en) Semiconductor device and lead frame used to manufacture semiconductor device
US8390105B2 (en) Lead frame substrate, manufacturing method thereof, and semiconductor apparatus
US9013030B2 (en) Leadframe, semiconductor package including a leadframe and method for producing a leadframe
US8558363B2 (en) Lead frame substrate and method of manufacturing the same, and semiconductor device
JP2005191240A (en) Semiconductor device and method for manufacturing the same
US20090212404A1 (en) Leadframe having mold lock vent
JP3664045B2 (en) Manufacturing method of semiconductor device
JP4600124B2 (en) Manufacturing method of semiconductor package
US6617200B2 (en) System and method for fabricating a semiconductor device
US7098081B2 (en) Semiconductor device and method of manufacturing the device
JP6752639B2 (en) Manufacturing method of semiconductor devices
JP3915794B2 (en) Semiconductor package, manufacturing method thereof, and lead frame used for the same
JP2008034830A (en) Semiconductor device, and lead frame and its manufacturing method
JP6080305B2 (en) Semiconductor device manufacturing method, semiconductor device, and lead frame
JP2005311137A (en) Semiconductor device, manufacturing method thereof, and lead frame thereof and mounting structure
KR100396869B1 (en) Junction method for a flexible printed circuit board
JP2006147918A (en) Semiconductor device
JP5104020B2 (en) Mold package
JP4840305B2 (en) Manufacturing method of semiconductor device
US20080210457A1 (en) Tape carrier for semiconductor device and method for making same
US20040119146A1 (en) Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
JP2003017628A (en) Resin-sealed semiconductor device
JP2010027459A (en) Battery pack manufacturing method
JP2004311667A (en) Semiconductor device, electronic device, and wiring board
JP2009071032A (en) Semiconductor apparatus and method of manufacturing the same

Legal Events

Date Code Title Description
RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7421

Effective date: 20091105

RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7421

Effective date: 20091113

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20100305

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100831

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120522

A761 Written withdrawal of application

Free format text: JAPANESE INTERMEDIATE CODE: A761

Effective date: 20120719