JPH04162466A - Lead frame for semiconductor device - Google Patents

Lead frame for semiconductor device

Info

Publication number
JPH04162466A
JPH04162466A JP2286097A JP28609790A JPH04162466A JP H04162466 A JPH04162466 A JP H04162466A JP 2286097 A JP2286097 A JP 2286097A JP 28609790 A JP28609790 A JP 28609790A JP H04162466 A JPH04162466 A JP H04162466A
Authority
JP
Japan
Prior art keywords
lead
view
lead frame
semiconductor device
product
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2286097A
Other languages
Japanese (ja)
Inventor
Tomotsune Sugiyama
杉山 智恒
Eiji Tsukiide
月出 英治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2286097A priority Critical patent/JPH04162466A/en
Publication of JPH04162466A publication Critical patent/JPH04162466A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a rigid mounting strength by forming at least a part to be cut of outer leads thinly. CONSTITUTION:A lead part 6 not used as an outer lead 4 is thinned as compared with an effective part as the lead 4, and formed as a product through assembling - finishing steps. In this case, outer layer solder plating is performed at almost all parts of the end side faces 8 of the leads 4 to be mounted. Accordingly, a rigid mounting strength is obtained at the time of mounting the product.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置用リードフレームに関し、特に実装
時の半田付性に優れた半導体装置用リードフレームに関
する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lead frame for a semiconductor device, and more particularly to a lead frame for a semiconductor device that has excellent solderability during mounting.

〔従来の技術〕[Conventional technology]

従来のこの種の半導体装置用リードフレームは、第3図
(a)及至第3図(d)に示す様な形状をしており、半
導体素子を半導体素子搭載台部に接合するグイボンディ
ング工程、インナーリード1と半導体素子の電極部とを
金属細線で接続するワイヤーボンディング工程、樹脂封
止ライン2に沿った樹脂封止工程、タイバー3の切断工
程。
A conventional lead frame for a semiconductor device of this type has a shape as shown in FIGS. 3(a) to 3(d), and includes a bonding process for bonding a semiconductor element to a semiconductor element mounting base, A wire bonding process for connecting the inner lead 1 and the electrode portion of the semiconductor element with a thin metal wire, a resin sealing process along the resin sealing line 2, and a tie bar 3 cutting process.

外装半田めっき工程、外部(アウター)リード4の切断
及び成形工程(第3図(C))を経て半導体製品として
完成する。
The semiconductor product is completed through an exterior solder plating process and an external (outer) lead 4 cutting and molding process (FIG. 3(C)).

前述の様な工程を経る為、外部リード4の半田付部7の
うち外部リード4の先端の側面部8は外装半田めっきが
施されていないまま、プリント基板等の被実装物に実装
されていた。
Because the process described above is carried out, the side surface portion 8 of the tip of the external lead 4 among the soldered portions 7 of the external lead 4 is mounted on an object to be mounted such as a printed circuit board without being subjected to exterior solder plating. Ta.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

前述した従来の半導体装置用リードフレームは、外部端
子リード4の底面の半田付部7には外装半田めっきが施
されているが、側面部8には外装半田めっきが施されて
いないので、プリント基板等の被実装物に実装する時、
実装強度不足になり、その半導体装置の持つ信頼性を著
しく劣化させる。
In the conventional lead frame for semiconductor devices described above, the solder portion 7 on the bottom of the external terminal lead 4 is coated with exterior solder plating, but the side portion 8 is not coated with solder plating, so it is difficult to print. When mounting on a mounted object such as a board,
This results in insufficient mounting strength and significantly deteriorates the reliability of the semiconductor device.

又、半田付後の実装検査では、リード先端の半田形状を
確認する事が多くなっているが、側面部8の半田付不良
が外見上発見できないことがある。
Furthermore, in the mounting inspection after soldering, the shape of the solder at the tip of the lead is often checked, but a soldering defect on the side surface 8 may not be found visually.

本発明の目的は、前記問題点を解決し、側面部の半田付
が良好に行えるようにした半導体装置用リードフレーム
を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a lead frame for a semiconductor device which solves the above-mentioned problems and allows good soldering of the side surface.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の構成は、インナーリード、アウターリードが多
数配列された半導体装置用リードフレームにおいて、前
記アウターリードのうち少なくとも切断される部分が細
く形成されていることを特徴とする。
The structure of the present invention is characterized in that in a lead frame for a semiconductor device in which a large number of inner leads and outer leads are arranged, at least a portion of the outer leads to be cut is formed to be thin.

〔実施例〕〔Example〕

次に図面を参照しながら本発明を説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(a)、第1図(b)は本発明の第1の実施例の
半導体装置用リードフし−ムを示す平面図、断面図、第
1図(c)はアウターリードの切断・加工後の側面図、
第1図(d)は第1図(c)の先端側面部を示す側面図
である。
FIGS. 1(a) and 1(b) are a plan view and a sectional view showing a lead frame for a semiconductor device according to a first embodiment of the present invention, and FIG. Side view after processing,
FIG. 1(d) is a side view showing the side surface of the tip of FIG. 1(c).

第1図<a)、(b)において、本実施例では、アウタ
ーリード4の切断予定線に沿って、講5を入れる。
In FIGS. 1A and 1B, in this embodiment, a cut 5 is inserted along the planned cutting line of the outer lead 4.

外部リード4の切断部5にスタンピング品ではノツチ、
エツチング品ではハーフエッチをそれぞれ施し、第1図
(c)に示す組立〜仕上工程を通り製品になるが、この
時外部リードの先端側面部8のほとんどの部分(第1図
(d))に外装半田めっきが施されて実装される。
The cut part 5 of the external lead 4 has a notch in the stamped product.
The etched product is half-etched and goes through the assembly to finishing process shown in FIG. 1(c) to become a product. Mounted with exterior solder plating.

第1図(d)の斜線部以外は、外装半田めっきを示す。The parts other than the shaded area in FIG. 1(d) show exterior solder plating.

第2図(a)、第2図(b)は本発明の第2の実施例の
半導体装置用リードフレームを示す平面図、断面図、第
2図(c)は第2図(b)のり−トフし−ムの切断加工
後の側面図、第2図(d)は第2図(c)の先端部の側
面図である。
FIGS. 2(a) and 2(b) are a plan view and a sectional view showing a lead frame for a semiconductor device according to a second embodiment of the present invention, and FIG. FIG. 2(d) is a side view of the tip of the top frame after cutting. FIG. 2(d) is a side view of the tip of FIG. 2(c).

第2図(a)、(b)において、本実施例では、外部リ
ード4として使用しないリード部分6を、外部リード4
として有効な部分より細くし、第2図(C)に示すよう
に、組立〜仕上工程を通り製品になるが、この時外部リ
ード4の先端側面図8のほとんどの部分(第2図(d)
)に、外装半田めっきが施されて実装される。
In FIGS. 2(a) and 2(b), in this embodiment, the lead portion 6 that is not used as the external lead 4 is
As shown in FIG. 2(C), the product is made thinner than the part that is effective as )
) is mounted with exterior solder plating.

第2図(d)の斜線部分以外は、外装半1田めっきを示
す。
The parts other than the shaded area in FIG. 2(d) show the exterior solder plating.

〔発明の効果〕〔Effect of the invention〕

以上説明した様に、本発明は、製品になった時の外部リ
ード先端の側面部に外装半田めっきが施される様な形状
にしたので、製品の実装時に強固な実装強度が得られ、
信頼性の高い製品を提供するという効果を有する。
As explained above, the present invention has a shape in which exterior solder plating is applied to the side surface of the tip of the external lead when the product is manufactured, so strong mounting strength can be obtained when the product is mounted.
This has the effect of providing highly reliable products.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)は本発明の第1の実施例の半導体装置用リ
ードフレームを示す平面図、第1図(b)は第1図(a
)の断面図、第1図(c)は第1図(b)のリードフレ
ームの切断加工後の状態を示す側面図、第1図(d)は
第1図(c)の先端部の側面図、第2図(a)は本発明
の第2の実施例の半導体装置用リードフレームを示す平
面図、第2図(b)は第2図(a)の断面図、第2図(
c)は第2図(b)のリードフレームの切断加工後の側
面図、第2図(d)は第2図(c)の先端部の側面図、
第3図(a)は従来のリードフレームの平面図、第3図
(b)は第3図(a)の断面図、第3図(c)は第3図
(b’ )の切断加工後の側面図、第3図(d)は第3
図(C)の先端部の側面図である。 1・・・複数のインナーリード、2−・・樹脂封止ライ
ン、3・・・タイバー、4−アウターリード、5・・・
講、6・・・細いアウターリード、7・・・外部リード
の半田付部、8・・・外部リードの先端側面部。
FIG. 1(a) is a plan view showing a lead frame for a semiconductor device according to a first embodiment of the present invention, and FIG. 1(b) is a plan view showing a lead frame for a semiconductor device according to a first embodiment of the present invention.
), FIG. 1(c) is a side view showing the state of the lead frame in FIG. 1(b) after cutting, and FIG. 1(d) is a side view of the tip of FIG. 1(c). 2(a) is a plan view showing a lead frame for a semiconductor device according to a second embodiment of the present invention, FIG. 2(b) is a sectional view of FIG. 2(a), and FIG.
c) is a side view of the lead frame in FIG. 2(b) after cutting, FIG. 2(d) is a side view of the tip of FIG. 2(c),
Figure 3(a) is a plan view of a conventional lead frame, Figure 3(b) is a cross-sectional view of Figure 3(a), and Figure 3(c) is a diagram of the cutting process shown in Figure 3(b'). The side view of Figure 3(d) is the side view of the third
It is a side view of the tip part of figure (C). 1... Multiple inner leads, 2... Resin sealing line, 3... Tie bar, 4- Outer lead, 5...
6...Thin outer lead, 7...Soldered part of the outer lead, 8...Tip side part of the outer lead.

Claims (1)

【特許請求の範囲】[Claims]  インナーリード、アウターリードが多数配列された半
導体装置用リードフレームにおいて、前記アウターリー
ドのうち少なくとも切断される部分が細く形成されてい
ることを特徴とする半導体装置用リードフレーム。
1. A lead frame for a semiconductor device in which a large number of inner leads and outer leads are arranged, wherein at least a portion of the outer lead to be cut is formed to be thin.
JP2286097A 1990-10-24 1990-10-24 Lead frame for semiconductor device Pending JPH04162466A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2286097A JPH04162466A (en) 1990-10-24 1990-10-24 Lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2286097A JPH04162466A (en) 1990-10-24 1990-10-24 Lead frame for semiconductor device

Publications (1)

Publication Number Publication Date
JPH04162466A true JPH04162466A (en) 1992-06-05

Family

ID=17699903

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2286097A Pending JPH04162466A (en) 1990-10-24 1990-10-24 Lead frame for semiconductor device

Country Status (1)

Country Link
JP (1) JPH04162466A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH051246U (en) * 1991-06-21 1993-01-08 山形日本電気株式会社 Lead frame for surface mount semiconductor device
JP2008034830A (en) * 2006-06-27 2008-02-14 Seiko Instruments Inc Semiconductor device, and lead frame and its manufacturing method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63250163A (en) * 1987-04-06 1988-10-18 Mitsubishi Electric Corp Semiconductor integrated circuit device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63250163A (en) * 1987-04-06 1988-10-18 Mitsubishi Electric Corp Semiconductor integrated circuit device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH051246U (en) * 1991-06-21 1993-01-08 山形日本電気株式会社 Lead frame for surface mount semiconductor device
JP2008034830A (en) * 2006-06-27 2008-02-14 Seiko Instruments Inc Semiconductor device, and lead frame and its manufacturing method

Similar Documents

Publication Publication Date Title
JP2936769B2 (en) Lead frame for semiconductor device
JPS62232948A (en) Lead frame
JP3008470B2 (en) Lead frame
JPH04162466A (en) Lead frame for semiconductor device
JP2583353B2 (en) Lead frame for semiconductor device
JPS6097654A (en) Sealed type semiconductor device
JP2586352B2 (en) Lead cutting equipment for semiconductor devices
JPH03104148A (en) Package for semiconductor integrated circuit
JPH0730042A (en) Lead frame, for semiconductor device, semiconductor device using same, and manufacture thereof
JPH03185754A (en) Semiconductor device
JPH05315517A (en) Semiconductor device
JPH02302068A (en) Transfer mold type hybrid integrated circuit
JP3230318B2 (en) Lead frame for semiconductor device
JP2934372B2 (en) Method for manufacturing surface mount type semiconductor device
JPH04103154A (en) Semiconductor device, manufacture thereof, and mounting method thereof
JPH0555436A (en) Lead frame for semiconductor device
JPH06334090A (en) Lead structure of resin sealed semiconductor device and manufacture thereof
JPH05291456A (en) Lead frame and processing method therefor
JPH05335437A (en) Semiconductor device
JP2002094125A (en) Lead frame and led device using the same
JPH0442934Y2 (en)
JPH033354A (en) Semiconductor device
JPS63110661A (en) Resin sealed package for semiconductor integrated circuit
JP2946775B2 (en) Resin sealing mold
JPH0574996A (en) Semiconductor sealed with resin