JPH04162466A - Lead frame for semiconductor device - Google Patents
Lead frame for semiconductor deviceInfo
- Publication number
- JPH04162466A JPH04162466A JP2286097A JP28609790A JPH04162466A JP H04162466 A JPH04162466 A JP H04162466A JP 2286097 A JP2286097 A JP 2286097A JP 28609790 A JP28609790 A JP 28609790A JP H04162466 A JPH04162466 A JP H04162466A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- view
- lead frame
- semiconductor device
- product
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 229910000679 solder Inorganic materials 0.000 abstract description 12
- 238000007747 plating Methods 0.000 abstract description 10
- 238000005520 cutting process Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 101100008049 Caenorhabditis elegans cut-5 gene Proteins 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007730 finishing process Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置用リードフレームに関し、特に実装
時の半田付性に優れた半導体装置用リードフレームに関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lead frame for a semiconductor device, and more particularly to a lead frame for a semiconductor device that has excellent solderability during mounting.
従来のこの種の半導体装置用リードフレームは、第３図
（ａ）及至第３図（ｄ）に示す様な形状をしており、半
導体素子を半導体素子搭載台部に接合するグイボンディ
ング工程、インナーリード１と半導体素子の電極部とを
金属細線で接続するワイヤーボンディング工程、樹脂封
止ライン２に沿った樹脂封止工程、タイバー３の切断工
程。A conventional lead frame for a semiconductor device of this type has a shape as shown in FIGS. 3(a) to 3(d), and includes a bonding process for bonding a semiconductor element to a semiconductor element mounting base, A wire bonding process for connecting the inner lead 1 and the electrode portion of the semiconductor element with a thin metal wire, a resin sealing process along the resin sealing line 2, and a tie bar 3 cutting process.
外装半田めっき工程、外部（アウター）リード４の切断
及び成形工程（第３図（Ｃ））を経て半導体製品として
完成する。The semiconductor product is completed through an exterior solder plating process and an external (outer) lead 4 cutting and molding process (FIG. 3(C)).
前述の様な工程を経る為、外部リード４の半田付部７の
うち外部リード４の先端の側面部８は外装半田めっきが
施されていないまま、プリント基板等の被実装物に実装
されていた。Because the process described above is carried out, the side surface portion 8 of the tip of the external lead 4 among the soldered portions 7 of the external lead 4 is mounted on an object to be mounted such as a printed circuit board without being subjected to exterior solder plating. Ta.
前述した従来の半導体装置用リードフレームは、外部端
子リード４の底面の半田付部７には外装半田めっきが施
されているが、側面部８には外装半田めっきが施されて
いないので、プリント基板等の被実装物に実装する時、
実装強度不足になり、その半導体装置の持つ信頼性を著
しく劣化させる。In the conventional lead frame for semiconductor devices described above, the solder portion 7 on the bottom of the external terminal lead 4 is coated with exterior solder plating, but the side portion 8 is not coated with solder plating, so it is difficult to print. When mounting on a mounted object such as a board,
This results in insufficient mounting strength and significantly deteriorates the reliability of the semiconductor device.
又、半田付後の実装検査では、リード先端の半田形状を
確認する事が多くなっているが、側面部８の半田付不良
が外見上発見できないことがある。Furthermore, in the mounting inspection after soldering, the shape of the solder at the tip of the lead is often checked, but a soldering defect on the side surface 8 may not be found visually.
本発明の目的は、前記問題点を解決し、側面部の半田付
が良好に行えるようにした半導体装置用リードフレーム
を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a lead frame for a semiconductor device which solves the above-mentioned problems and allows good soldering of the side surface.
本発明の構成は、インナーリード、アウターリードが多
数配列された半導体装置用リードフレームにおいて、前
記アウターリードのうち少なくとも切断される部分が細
く形成されていることを特徴とする。The structure of the present invention is characterized in that in a lead frame for a semiconductor device in which a large number of inner leads and outer leads are arranged, at least a portion of the outer leads to be cut is formed to be thin.
次に図面を参照しながら本発明を説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）、第１図（ｂ）は本発明の第１の実施例の
半導体装置用リードフし−ムを示す平面図、断面図、第
１図（ｃ）はアウターリードの切断・加工後の側面図、
第１図（ｄ）は第１図（ｃ）の先端側面部を示す側面図
である。FIGS. 1(a) and 1(b) are a plan view and a sectional view showing a lead frame for a semiconductor device according to a first embodiment of the present invention, and FIG. Side view after processing,
FIG. 1(d) is a side view showing the side surface of the tip of FIG. 1(c).
第１図＜ａ）、（ｂ）において、本実施例では、アウタ
ーリード４の切断予定線に沿って、講５を入れる。In FIGS. 1A and 1B, in this embodiment, a cut 5 is inserted along the planned cutting line of the outer lead 4.
外部リード４の切断部５にスタンピング品ではノツチ、
エツチング品ではハーフエッチをそれぞれ施し、第１図
（ｃ）に示す組立〜仕上工程を通り製品になるが、この
時外部リードの先端側面部８のほとんどの部分（第１図
（ｄ））に外装半田めっきが施されて実装される。The cut part 5 of the external lead 4 has a notch in the stamped product.
The etched product is half-etched and goes through the assembly to finishing process shown in FIG. 1(c) to become a product. Mounted with exterior solder plating.
第１図（ｄ）の斜線部以外は、外装半田めっきを示す。The parts other than the shaded area in FIG. 1(d) show exterior solder plating.
第２図（ａ）、第２図（ｂ）は本発明の第２の実施例の
半導体装置用リードフレームを示す平面図、断面図、第
２図（ｃ）は第２図（ｂ）のり−トフし−ムの切断加工
後の側面図、第２図（ｄ）は第２図（ｃ）の先端部の側
面図である。FIGS. 2(a) and 2(b) are a plan view and a sectional view showing a lead frame for a semiconductor device according to a second embodiment of the present invention, and FIG. FIG. 2(d) is a side view of the tip of the top frame after cutting. FIG. 2(d) is a side view of the tip of FIG. 2(c).
第２図（ａ）、（ｂ）において、本実施例では、外部リ
ード４として使用しないリード部分６を、外部リード４
として有効な部分より細くし、第２図（Ｃ）に示すよう
に、組立〜仕上工程を通り製品になるが、この時外部リ
ード４の先端側面図８のほとんどの部分（第２図（ｄ）
）に、外装半田めっきが施されて実装される。In FIGS. 2(a) and 2(b), in this embodiment, the lead portion 6 that is not used as the external lead 4 is
As shown in FIG. 2(C), the product is made thinner than the part that is effective as )
) is mounted with exterior solder plating.
第２図（ｄ）の斜線部分以外は、外装半１田めっきを示
す。The parts other than the shaded area in FIG. 2(d) show the exterior solder plating.
以上説明した様に、本発明は、製品になった時の外部リ
ード先端の側面部に外装半田めっきが施される様な形状
にしたので、製品の実装時に強固な実装強度が得られ、
信頼性の高い製品を提供するという効果を有する。As explained above, the present invention has a shape in which exterior solder plating is applied to the side surface of the tip of the external lead when the product is manufactured, so strong mounting strength can be obtained when the product is mounted.
This has the effect of providing highly reliable products.
第１図（ａ）は本発明の第１の実施例の半導体装置用リ
ードフレームを示す平面図、第１図（ｂ）は第１図（ａ
）の断面図、第１図（ｃ）は第１図（ｂ）のリードフレ
ームの切断加工後の状態を示す側面図、第１図（ｄ）は
第１図（ｃ）の先端部の側面図、第２図（ａ）は本発明
の第２の実施例の半導体装置用リードフレームを示す平
面図、第２図（ｂ）は第２図（ａ）の断面図、第２図（
ｃ）は第２図（ｂ）のリードフレームの切断加工後の側
面図、第２図（ｄ）は第２図（ｃ）の先端部の側面図、
第３図（ａ）は従来のリードフレームの平面図、第３図
（ｂ）は第３図（ａ）の断面図、第３図（ｃ）は第３図
（ｂ’ ）の切断加工後の側面図、第３図（ｄ）は第３
図（Ｃ）の先端部の側面図である。
１・・・複数のインナーリード、２−・・樹脂封止ライ
ン、３・・・タイバー、４−アウターリード、５・・・
講、６・・・細いアウターリード、７・・・外部リード
の半田付部、８・・・外部リードの先端側面部。FIG. 1(a) is a plan view showing a lead frame for a semiconductor device according to a first embodiment of the present invention, and FIG. 1(b) is a plan view showing a lead frame for a semiconductor device according to a first embodiment of the present invention.
), FIG. 1(c) is a side view showing the state of the lead frame in FIG. 1(b) after cutting, and FIG. 1(d) is a side view of the tip of FIG. 1(c). 2(a) is a plan view showing a lead frame for a semiconductor device according to a second embodiment of the present invention, FIG. 2(b) is a sectional view of FIG. 2(a), and FIG.
c) is a side view of the lead frame in FIG. 2(b) after cutting, FIG. 2(d) is a side view of the tip of FIG. 2(c),
Figure 3(a) is a plan view of a conventional lead frame, Figure 3(b) is a cross-sectional view of Figure 3(a), and Figure 3(c) is a diagram of the cutting process shown in Figure 3(b'). The side view of Figure 3(d) is the side view of the third
It is a side view of the tip part of figure (C). 1... Multiple inner leads, 2... Resin sealing line, 3... Tie bar, 4- Outer lead, 5...
6...Thin outer lead, 7...Soldered part of the outer lead, 8...Tip side part of the outer lead.
Claims (1)
導体装置用リードフレームにおいて、前記アウターリー
ドのうち少なくとも切断される部分が細く形成されてい
ることを特徴とする半導体装置用リードフレーム。1. A lead frame for a semiconductor device in which a large number of inner leads and outer leads are arranged, wherein at least a portion of the outer lead to be cut is formed to be thin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2286097A JPH04162466A (en) | 1990-10-24 | 1990-10-24 | Lead frame for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2286097A JPH04162466A (en) | 1990-10-24 | 1990-10-24 | Lead frame for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04162466A true JPH04162466A (en) | 1992-06-05 |
Family
ID=17699903
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2286097A Pending JPH04162466A (en) | 1990-10-24 | 1990-10-24 | Lead frame for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04162466A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH051246U (en) * | 1991-06-21 | 1993-01-08 | 山形日本電気株式会社 | Lead frame for surface mount semiconductor device |
| JP2008034830A (en) * | 2006-06-27 | 2008-02-14 | Seiko Instruments Inc | Semiconductor device, and lead frame and its manufacturing method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63250163A (en) * | 1987-04-06 | 1988-10-18 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
-
1990
- 1990-10-24 JP JP2286097A patent/JPH04162466A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63250163A (en) * | 1987-04-06 | 1988-10-18 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH051246U (en) * | 1991-06-21 | 1993-01-08 | 山形日本電気株式会社 | Lead frame for surface mount semiconductor device |
| JP2008034830A (en) * | 2006-06-27 | 2008-02-14 | Seiko Instruments Inc | Semiconductor device, and lead frame and its manufacturing method |
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