JP2583353B2 - Lead frame for semiconductor device - Google Patents
Lead frame for semiconductor deviceInfo
- Publication number
- JP2583353B2 JP2583353B2 JP2299523A JP29952390A JP2583353B2 JP 2583353 B2 JP2583353 B2 JP 2583353B2 JP 2299523 A JP2299523 A JP 2299523A JP 29952390 A JP29952390 A JP 29952390A JP 2583353 B2 JP2583353 B2 JP 2583353B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- lead
- lead frame
- external
- cut
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置用リードフレームに関し、特に外
部リードの形状に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame for a semiconductor device, and particularly to a shape of an external lead.
従来の半導体装置では、第３図（ａ）に示すように、
放射状に広がっている多数の外部リード３が、タイバー
部２及びフレーム部１で互いに連結されており、その間
は凹部を有さないストレートな平面形状で構成されてい
る。第３図（ｂ）において、半導体素子11は、アイラン
ド４に固着された後、樹脂封止によりパッケージ部５が
構成される。その後、外部リード３の半田付性を良好な
ものとする為に、この外部リード３に鉛又は錫・鉛合金
めっき７が施される。半導体装置は、その後タイバー部
２が切断され、外部リード先端が第３図（ａ）の破線ａ
の位置で切断され、第３図（ｂ）の状態となり、そして
外部リード３は曲げ加工され、第３図（ｃ）の状態とな
る。In a conventional semiconductor device, as shown in FIG.
A large number of radially extending external leads 3 are connected to each other by a tie bar portion 2 and a frame portion 1, and have a straight planar shape having no concave portion therebetween. In FIG. 3B, after the semiconductor element 11 is fixed to the island 4, the package portion 5 is formed by resin sealing. Thereafter, in order to improve the solderability of the external lead 3, the external lead 3 is coated with lead or tin / lead alloy plating 7. In the semiconductor device, the tie bar portion 2 is thereafter cut, and the tip of the external lead is set to the broken line a in FIG.
3 (b), and the external lead 3 is bent to obtain the state shown in FIG. 3 (c).
完成した半導体装置は、第３図（ｄ）に示すように、
プリント基板10に半田付実装される。切断分離した後の
外部リード３の先端部８の切断面には、外装めっき７が
被覆していない。その為、半田付実装後の半田メニスカ
ス９は、第３図（ｄ）に示すように小さく、リード先端
部の半田付性が悪い。The completed semiconductor device is as shown in FIG.
The printed circuit board 10 is mounted by soldering. The outer plating 7 does not cover the cut surface of the distal end portion 8 of the external lead 3 after cutting and separation. Therefore, the solder meniscus 9 after soldering and mounting is small as shown in FIG. 3D, and the solderability of the lead tip is poor.
従来の半導体装置のリードフレームでは、外部リード
３の先端を形成するために切断分離を行った場合、切断
面には錫、或は錫・鉛合金の外装めっきが被覆していな
い。In a conventional lead frame of a semiconductor device, when cut and separated to form the tip of the external lead 3, the cut surface is not covered with tin or a tin-lead alloy exterior plating.
そのため、切断面の半田濡れが悪く、半田付強度が劣
化すると共に、半田付後の外観検査において、リード先
端方向から半田メニスカス９を認識することが難しく正
確な検査ができないという問題点があった。Therefore, there is a problem that the solder wettability of the cut surface is poor, the soldering strength is deteriorated, and in the appearance inspection after the soldering, it is difficult to recognize the solder meniscus 9 from the leading end of the lead, so that an accurate inspection cannot be performed. .
本発明の目的は、前記問題点を解決し、リード先端部
の半田付性が良好になるようにした半導体装置用リード
フレームを提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a lead frame for a semiconductor device which solves the above-mentioned problems and improves the solderability of a lead end portion.
本発明の特徴は、アイランドが露出している状態の封
入前のリードフレームにおいて、半導体装置の外部リー
ド先端を形成する切断分離予定位置に、実装時に基板に
接続する側の主面から、内部に立ち上がる側部をアイラ
ンド側に有しかつその底部が薄い板厚となる凹部を設け
た半導体装置用リードフレームにある。A feature of the present invention is that, in a pre-encapsulated lead frame in a state where an island is exposed, a cut-separation position forming an end of an external lead of a semiconductor device is moved from a main surface on a side connected to a substrate during mounting to an inside thereof. There is provided a semiconductor device lead frame having a rising side on an island side and a bottom provided with a concave portion having a small thickness.
次に本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図（ａ）は本発明の一実施例の半導体装置用リー
ドフレームの平面図である。FIG. 1A is a plan view of a lead frame for a semiconductor device according to one embodiment of the present invention.
第１図（ａ）において、本実施例のリードフレーム
は、外部リード３の切断分離位置に、厚み方向の凹部を
有する。外部リード３の切断分離位置を破線ａで示して
いる。第１図（ｂ）に示すように、凹部６が形成されて
おり、このほぼ中央線の破線ａで切断される。この切断
の前に、外装めっき７が両主面に施される。In FIG. 1A, the lead frame of the present embodiment has a concave portion in the thickness direction at a cutting and separating position of the external lead 3. The broken separation position of the external lead 3 is indicated by a broken line a. As shown in FIG. 1 (b), a concave portion 6 is formed, and is cut by a substantially broken center line a. Before this cutting, exterior plating 7 is applied to both main surfaces.
第１図（ｃ）に示すように、封入後、外装めっき７を
施した半導体装置の断面図である。第１図（ｄ）に示す
ように、リードの曲げ工程を経た後の半導体装置を、基
板10に半田付実装した場合が示されている。外装めっき
７は、外部リード３の凹部６にも被覆されている為、半
田メニスカス９が広がり、半田濡れが良くなっており、
半田付強度も向上する。FIG. 1C is a cross-sectional view of the semiconductor device in which the outer plating 7 is applied after encapsulation, as shown in FIG. FIG. 1D shows a case where the semiconductor device after the bending process of the lead is mounted on the substrate 10 by soldering. Since the exterior plating 7 is also coated on the recess 6 of the external lead 3, the solder meniscus 9 spreads and solder wetting is improved,
The soldering strength is also improved.
以上、第３図（ａ）乃至第３図（ｄ）と、本実施例と
が同様の部分については、説明を割愛した。The description of the same parts as those of the present embodiment from FIGS. 3 (a) to 3 (d) has been omitted.
続いて第２図を参照して、本発明に関係する技術のリ
ードフレームを説明する。第２図（ａ）はそのリードフ
レームの平面図であり、同図においてリードフレームの
外部リード３の切断分離予定位置に幅方向の凹部６′を
有する。この場合、外部リード３は破線ａの位置で切断
分離がなされ、その形状は第２図（ｂ）の様になる。第
２図（ｂ）のB1−B2線の断面を、第２図（ｃ）に示す。
第２図のリードフレームのリード先端部８には、外装め
っき７は施されていないが、凹部６′の先端部８−ａに
はめっきが施されており、前記実施例と同様の効果を有
する。Subsequently, a lead frame of a technique related to the present invention will be described with reference to FIG. FIG. 2 (a) is a plan view of the lead frame. In FIG. 2 (a), the lead frame has a recess 6 'in the width direction at a position where the external lead 3 is to be cut and separated. In this case, the external lead 3 is cut and separated at the position of the broken line a, and its shape is as shown in FIG. 2 (b). FIG. 2 (c) shows a cross section taken along line B1-B2 in FIG. 2 (b).
The lead end portion 8 of the lead frame shown in FIG. 2 is not coated with the exterior plating 7, but the end portion 8-a of the concave portion 6 'is plated. Have.
以上説明したように、本発明は、リードフレームの外
部リードを形成するために切断分離を行う位置に、凹部
を設けたことによって、リード先端の半田濡れ性が良く
なり、半田付強度が向上するという効果を有する。As described above, the present invention improves the solder wettability at the tip of the lead and improves the soldering strength by providing the recess at the position where the cutting and separation are performed to form the external lead of the lead frame. It has the effect of.
第１図（ａ）は本発明の一実施例の半導体装置用リード
フレームを示す平面図、第１図（ｂ）は第１図（ａ）の
凹部のある外部リードの断面図、第１図（ｃ）は第１図
（ｂ）の外部リードをめっきし、切断した状態を示す断
面図、第１図（ｄ）は第１図（ｃ）の外部リードを基板
に半田付けした状態を示す断面図、第２図（ａ）は本発
明に関係のあるリードフレームを示す平面図、第２図
（ｂ）は第２図（ａ）のリードフレームを切断後の状態
を示す斜視図、第２図（ｃ）は第２図（ｂ）のB1−B2線
に沿って切断して見た断面図、第３図（ａ）は従来のリ
ードフレームを示す平面図、第３図（ｂ）乃至第３図
（ｄ）は従来の半導体装置用リードフレームを用いて、
半導体装置を製造し、実装する状態を順に示した断面図
である。 １……フレーム部、２……タイバー部、３……外部リー
ド、４……アイランド、５……樹脂封止部、6,6′……
凹部、７……外装めっき、8,8a……外部リード先端、９
……半田メニスカス、10……プリント基板。1A is a plan view showing a lead frame for a semiconductor device according to one embodiment of the present invention, FIG. 1B is a cross-sectional view of an external lead having a recess shown in FIG. 1A, FIG. (C) is a cross-sectional view showing a state where the external leads of FIG. 1 (b) are plated and cut, and FIG. 1 (d) shows a state where the external leads of FIG. 1 (c) are soldered to a substrate. FIG. 2 (a) is a plan view showing a lead frame related to the present invention, FIG. 2 (b) is a perspective view showing a state after cutting the lead frame of FIG. 2 (a), and FIG. 2 (c) is a sectional view taken along the line B1-B2 of FIG. 2 (b), FIG. 3 (a) is a plan view showing a conventional lead frame, and FIG. 3 (b) FIG. 3 (d) shows a conventional semiconductor device lead frame,
FIG. 4 is a cross-sectional view illustrating a state in which the semiconductor device is manufactured and mounted in order. 1 ... frame part, 2 ... tie bar part, 3 ... external lead, 4 ... island, 5 ... resin sealing part, 6, 6 '...
Recessed part, 7 ... external plating, 8, 8a ... external lead tip, 9
…… Solder meniscus, 10 …… Printed circuit board.
Claims (1)
リードフレームにおいて、半導体装置の外部リード先端
を形成する切断分離予定位置に、実装時に基板に接続す
る側の主面から、内部に立ち上がる側部をアイランド側
に有しかつその底部が薄い板厚となる凹部を設けたこと
を特徴とする半導体装置用リードフレーム。1. A lead frame before encapsulation in which an island is exposed, rises inward from a main surface on a side connected to a substrate at the time of mounting at a cut / separation scheduled position forming a tip of an external lead of a semiconductor device. A lead frame for a semiconductor device having a side portion on the island side and a concave portion having a bottom portion having a small thickness.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2299523A JP2583353B2 (en) | 1990-11-05 | 1990-11-05 | Lead frame for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2299523A JP2583353B2 (en) | 1990-11-05 | 1990-11-05 | Lead frame for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04171854A JPH04171854A (en) | 1992-06-19 |
| JP2583353B2 true JP2583353B2 (en) | 1997-02-19 |
Family
ID=17873697
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2299523A Expired - Fee Related JP2583353B2 (en) | 1990-11-05 | 1990-11-05 | Lead frame for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2583353B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH065767A (en) * | 1992-06-23 | 1994-01-14 | Nec Kyushu Ltd | Lead frame for semiconductor device |
| JP3666594B2 (en) | 2002-10-17 | 2005-06-29 | ローム株式会社 | Cutting method of lead terminals in package type electronic components |
| JP5614484B1 (en) * | 2013-09-20 | 2014-10-29 | 第一精工株式会社 | Joining member for electrical connector and method for manufacturing the same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63127168U (en) * | 1987-02-12 | 1988-08-19 | ||
| JPH03104148A (en) * | 1989-09-18 | 1991-05-01 | Mitsubishi Electric Corp | Package for semiconductor integrated circuit |
-
1990
- 1990-11-05 JP JP2299523A patent/JP2583353B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04171854A (en) | 1992-06-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |