JPS62169354A - Packaging structure of semiconductor device - Google Patents
Packaging structure of semiconductor deviceInfo
- Publication number
- JPS62169354A JPS62169354A JP30370786A JP30370786A JPS62169354A JP S62169354 A JPS62169354 A JP S62169354A JP 30370786 A JP30370786 A JP 30370786A JP 30370786 A JP30370786 A JP 30370786A JP S62169354 A JPS62169354 A JP S62169354A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- tip
- solder
- sides
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 238000004806 packaging method and process Methods 0.000 title abstract description 3
- 238000005476 soldering Methods 0.000 claims abstract description 3
- 229910000679 solder Inorganic materials 0.000 abstract description 38
- 230000001070 adhesive effect Effects 0.000 abstract description 3
- 238000007747 plating Methods 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- 238000005219 brazing Methods 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置実装構造に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device mounting structure.
半導体装置を実装基板に実装する場合、近年では実装基
板に形成した回路上にリードを接触させてこれを半田等
によりろう付けする所謂片面搭載による取付が行なわれ
ている。これは、主にフラットパッケージ型の半導体装
置に施されることが多く、従来のディアルインライン型
の半導体のようにリードを基板に貫通させてリード周囲
をろう付ける構造と比較して、実装スペース（厚さ寸法
）が低減でき、高密度の実装を可能にするという利点が
ある。When mounting a semiconductor device on a mounting board, in recent years, so-called single-sided mounting has been carried out in which leads are brought into contact with circuits formed on the mounting board and then brazed with solder or the like. This is mainly applied to flat package type semiconductor devices, and compared to the structure of conventional dual-in-line type semiconductors in which the leads penetrate the board and the area around the leads is brazed, the mounting space ( This has the advantage that the thickness dimension) can be reduced and high-density packaging is possible.
このような片面搭載を行なうため、従来では第１図に示
すように、パッケージｌから突出されたリード２の先端
２ａを実装基板３面と平行になるように略９０°折曲し
、この先端部２ａを基板表面に形成した回路上に乗せて
、両者を半田４付けしている。この場合、通常では回路
には半田印刷を施しており、この半田を溶融さＵｏると
同時にリード先端部２ａを回路の半田４上に押圧するこ
とによって半田付か行なわれるようになっている。In order to carry out such single-sided mounting, conventionally, as shown in FIG. The portion 2a is placed on a circuit formed on the surface of the substrate, and both are soldered 4. In this case, the circuit is usually printed with solder, and soldering is carried out by melting the solder and simultaneously pressing the lead tip 2a onto the solder 4 of the circuit.
上に述べたこのリード先端部２ａの構造では、先端部と
回路との接触面積は大きくとれるものの、この接触面積
の大きいことがかえって逆に作用して先端部２ａ上側面
への半田の回り込みが抑制され、接着性に充分満足でき
るものが得られないという問題が生じている。即ち、先
端部２ａの接触面積が大きいため、先端部２ａを溶融半
田上に押圧すると、半田は左右方向へ押しやられ同時に
半田には表面張力が作用して球面状になろうとするため
、押しやられた半田が先端部２ａの上面にまで回り込ん
で接着することが困難になるためである。Although the structure of the lead tip 2a described above allows for a large contact area between the tip and the circuit, this large contact area has the opposite effect and prevents solder from wrapping around the upper surface of the tip 2a. The problem has arisen that it is difficult to obtain a product with sufficiently satisfactory adhesion properties. That is, since the contact area of the tip 2a is large, when the tip 2a is pressed onto the molten solder, the solder is pushed in the left and right direction, and at the same time, surface tension acts on the solder and tries to take on a spherical shape, so it is pushed away. This is because the solder spreads to the upper surface of the tip portion 2a, making it difficult to bond it.
また、このように接触面積が大きいと、先端部２ａと回
路の半田４との接着面における半田の濡れ性を外観から
確認或いは検査することが難かしいという問題もある。Further, when the contact area is large as described above, there is also a problem that it is difficult to visually confirm or inspect the wettability of the solder on the adhesive surface between the tip portion 2a and the solder 4 of the circuit.
なお、リード先端面でろう付けする方法が特開昭５２−
７２１６６号公報によって知られている。In addition, the method of brazing the lead end surface is disclosed in Japanese Patent Application Laid-Open No. 1973-
It is known from the publication No. 72166.
しかしながら、後述するようにリード側面と半田との接
触性が不充分である。However, as will be described later, the contact between the lead side surface and the solder is insufficient.
本発明の目的は半田等のろう材との濡れ性が良好で実装
基板とめ接着性がよい半導体装置の実装構造を提供する
ことにある。An object of the present invention is to provide a mounting structure for a semiconductor device that has good wettability with a brazing material such as solder and has good adhesion to a mounting board.
このような目的を達成するために本発明は、半導体装置
のリードを実装基板面に当接してろう付けするようにし
た半導体装置の実装構造において、リード先端の両側に
は傾斜面をもち、そのリードの先端面および両側の傾斜
面に対してろう付けがされてなることを特徴とするらの
である。In order to achieve such an object, the present invention provides a mounting structure for a semiconductor device in which the leads of the semiconductor device are brazed in contact with the surface of the mounting board, in which the leads have sloped surfaces on both sides. It is characterized in that the tip end face of the lead and the sloped faces on both sides are brazed.
本発明によれば、ろう材がリードの先端面および傾斜面
に充分濡れるためにリード実装基板との接着性が良好と
なる。According to the present invention, since the brazing material sufficiently wets the tip end surface and the inclined surface of the lead, the adhesion to the lead mounting board is improved.
第２図は本発明のリード構造を有するフラットパッケー
ジ型半導体装置の要部斜視図であり、図において、Ｉｆ
は半導体ペレットやこの半導体とリードとを接続するワ
イヤ等をレジンモールド等にて封止したパッケージ、１
２はこのパッケージｌｌ内にインナーリードをモールド
さ仕、パッケージ１１の四周側からアウターリード１３
を突出させた複数本のリードである。このリード１２は
パッケージ１１からは横方向に向って突出されているが
すぐ下方に向って略直角に折曲しており、更に、このリ
ード１２の先端面１４は実装基板１５の実装面に形成し
た半田印刷回路１６の上面に略垂直方向に当接するよう
になっている。前記リード１２の先端部Ｉ４の形状は、
第３図に合わせて示すように、先端面の中央部Ｉ７を幾
分残してその両側を削成し、先端面或いは両側面に対し
て所定の角度θ。をらった傾斜面１８として構成してい
る。そして、これら先端面中央部１７と傾斜面１８には
半田めっき等を行なって表面に半田塗膜を形成している
のである。FIG. 2 is a perspective view of a main part of a flat package type semiconductor device having a lead structure according to the present invention.
1 is a package in which a semiconductor pellet and wires connecting the semiconductor and leads are sealed in a resin mold, etc.
2 molds inner leads in this package 11, and inserts outer leads 13 from the four circumferential sides of the package 11.
There are multiple leads that stand out. This lead 12 protrudes laterally from the package 11, but is bent downward at a substantially right angle.Furthermore, the tip end surface 14 of this lead 12 is formed on the mounting surface of the mounting board 15. The solder printed circuit 16 is brought into contact with the top surface of the soldered printed circuit 16 in a substantially vertical direction. The shape of the tip I4 of the lead 12 is as follows:
As shown in FIG. 3, both sides of the distal end surface are cut away leaving some of the central portion I7 at a predetermined angle θ with respect to the distal end surface or both side surfaces. It is configured as a sloped surface 18 with a curved surface. The central portion 17 of the tip end face and the inclined surface 18 are subjected to solder plating or the like to form a solder coating film on the surface.
以上の構成によれば、半導体装置の実装に際しては、第
４図に示すように、加熱されて溶融状態にある半田印刷
回路１６上に略垂直方向にリード１２先端を当接し、更
にこれを仮想線のように押込んでゆくと、それだけで印
刷回路の半田１６はリード１２の先端面中央部Ｉ７はも
とより傾斜面１８とも良好に濡れた状態となり、同図の
ように両側の半田が盛り上るようにしてリード先端をろ
う付けするのである。したがって、実装板１５へのり一
ド１２のろう付けを強固に行ない得ると共に、リード先
端部は実装板に対して略垂直方向に接続されているので
接続状態の外観判断を比較的容易に行なうことができる
。According to the above configuration, when mounting a semiconductor device, as shown in FIG. By pushing it in like a line, the solder 16 of the printed circuit will become well wetted not only at the center part I7 of the tip surface of the lead 12 but also on the inclined surface 18, and the solder on both sides will swell up as shown in the figure. Then, the tip of the lead is brazed. Therefore, the adhesive 12 can be firmly brazed to the mounting board 15, and since the lead ends are connected in a direction substantially perpendicular to the mounting board, it is relatively easy to visually judge the connection state. I can do it.
更に、リード先端面中央部１７と傾斜面１８には予め半
田めっき等によって半田塗膜を形成しているため、回路
印刷の半田との濡れ性は更に向上する。尚、リードの前
後面１９．２０（第２図参照）の先端部にも半田塗膜を
形成しておけば、前後面における濡れ性の向上にも有効
である。Further, since a solder coating film is previously formed on the center portion 17 of the lead end face and the inclined surface 18 by solder plating or the like, wettability with solder for circuit printing is further improved. Incidentally, if a solder coating film is also formed on the tips of the front and rear surfaces 19 and 20 (see FIG. 2) of the lead, it is effective to improve the wettability on the front and rear surfaces.
ここで、前記リード■２の半田との濡れ性を考察する。Here, the wettability of the lead (2) with solder will be considered.
一般に半田は溶融状態で表面張力が大きく、実装板上で
球面状態になろうとする。この性質はリード先端部が半
田上に当接されかつ押込まれたときにも表われ、押込ま
れたリードの両側に押分けられた半田も夫々表面張力に
より球面状態になろうとする。このとき、第５図（Ａ）
、（Ｂ）に比較図示するように、側面１８°が垂直の（
Ａ）の状態（萌述の特開昭５２−７２１６６号公報に開
示）では側面と半田＋６’との接触性はあまり良好では
ないが、（Ｂ）のように側面１８か傾斜していると側面
は半田Ｉ６の球面に近接して接触性は良好になる。した
がって、前記実施例における傾斜面Ｉ８の傾斜角θ。は
半田の接触角θ１に近似する値が好ましい。Generally, solder has a large surface tension in its molten state and tends to form a spherical shape on the mounting board. This property also appears when the tip of the lead is brought into contact with the solder and pushed in, and the solder pushed out on both sides of the pushed lead also tends to form a spherical shape due to surface tension. At this time, Fig. 5 (A)
, as shown in the comparative diagram in (B), the side surface 18° is vertical (
In the state of A) (disclosed in Japanese Patent Application Laid-Open No. 52-72166 by Moejo), the contact between the side surface and the solder +6' is not very good, but when the side surface 18 is inclined as shown in (B), The side surfaces are close to the spherical surface of the solder I6 and have good contact. Therefore, the inclination angle θ of the inclined surface I8 in the embodiment. is preferably a value that approximates the solder contact angle θ1.
また、リード先端部１４を半田に押込んでゆくときに、
リード面と半田とを衝突させる方が接着性は良好になる
ことから、傾斜面１８を形成してリードと半田との衝突
面積を増大することも半田との濡れを良好にする理由と
なっている。したがって、先端面中央部１７の面積と傾
斜面１８の面積（但し、半田の厚さを考慮した実質的な
傾斜面積）の和が最大となるようにこれらを定めればよ
く、実際上はリード全中寸法に対する中央部の巾寸法を
約１７３若しくはこれよりも若干大きくすればよい。Also, when pushing the lead tip 14 into the solder,
Since adhesion is better when the lead surface collides with the solder, forming the inclined surface 18 to increase the collision area between the lead and the solder also improves wetting with the solder. There is. Therefore, the sum of the area of the central portion 17 of the tip surface and the area of the inclined surface 18 (however, the actual inclined area considering the thickness of the solder) may be determined to be the maximum, and in practice, the lead The width dimension of the center portion relative to the entire middle dimension may be approximately 173 mm or slightly larger than this.
尚、第６図に示すように、傾斜面を規定する傾斜角θＸ
を順次変化させて、傾斜面を凹曲面１８Ａとして形成し
てもよい。このようにすれば、凹曲面１８Ａは半田の球
面に沿うようになり、接着性を一段と向上することがで
きる。Incidentally, as shown in FIG. 6, the inclination angle θX defining the inclined surface
The inclined surface may be formed as the concave curved surface 18A by sequentially changing the curved surface. In this way, the concave curved surface 18A will follow the spherical surface of the solder, and the adhesiveness can be further improved.
以上の説明のように本発明のリード構造は、リード先端
部の両側に先端面に対して傾斜した傾斜面を形成し、か
つろう材の塗膜を形成しているので、構造が極めて簡単
でありながらろう材との濡れ性が向上して良好な接続構
造を得ることができると共に、接続状態の外観検査を容
易に行なうことができる等の効果を奏する。As explained above, the lead structure of the present invention has an extremely simple structure because it has sloped surfaces on both sides of the lead tip that are inclined with respect to the tip surface, and a coating film of brazing material. However, the wettability with the brazing material is improved and a good connection structure can be obtained, and the appearance of the connection state can be easily inspected.
第１図は従来のリード構造の側面図、第２図は本発明の
リード構造を示す半導体装置の要部斜視図、第３図はリ
ード先端部の拡大正面図、第４図はろう付状態を示す正
面図、第５図（Ａ）、（Ｂ）は濡れ性を比較した模式的
正面図、第６図は他ま実施例のリード先端部の拡大正面
図である。
１１・・・半導体パッケージ、１２・・・リート、ｉ４
・・・先端部、１５・・・実装基板、１６・・・回路印
刷半田。Fig. 1 is a side view of a conventional lead structure, Fig. 2 is a perspective view of the main parts of a semiconductor device showing the lead structure of the present invention, Fig. 3 is an enlarged front view of the lead tip, and Fig. 4 is a brazed state. FIGS. 5(A) and 5(B) are schematic front views comparing wettability, and FIG. 6 is an enlarged front view of the lead tip of another example. 11... Semiconductor package, 12... REIT, i4
... Tip part, 15 ... Mounting board, 16 ... Circuit printed solder.
Claims (1)
けするようにした半導体装置の実装構造において、リー
ド先端の両側には傾斜面をもち、そのリードの先端面お
よび両側の傾斜面に対してろう付けがされてなることを
特徴とする半導体装置の実装構造。1. In a semiconductor device mounting structure in which the leads of the semiconductor device are brazed in contact with the surface of the mounting board, the lead tips have sloped surfaces on both sides, and A mounting structure for a semiconductor device characterized by being formed by soldering.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30370786A JPS62169354A (en) | 1986-12-22 | 1986-12-22 | Packaging structure of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30370786A JPS62169354A (en) | 1986-12-22 | 1986-12-22 | Packaging structure of semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP133480A Division JPS5698853A (en) | 1980-01-11 | 1980-01-11 | Structure of lead in semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62169354A true JPS62169354A (en) | 1987-07-25 |
| JPH0321096B2 JPH0321096B2 (en) | 1991-03-20 |
Family
ID=17924283
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30370786A Granted JPS62169354A (en) | 1986-12-22 | 1986-12-22 | Packaging structure of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62169354A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008166630A (en) * | 2006-12-29 | 2008-07-17 | Jst Mfg Co Ltd | Mounting member and its manufacturing method |
| JP2013051373A (en) * | 2011-08-31 | 2013-03-14 | Fujifilm Corp | Method for manufacturing electronic device |
| US20220157699A1 (en) * | 2019-03-18 | 2022-05-19 | Ampleon Netherlands B.V. | Electronic Molded Package |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5698853A (en) * | 1980-01-11 | 1981-08-08 | Hitachi Ltd | Structure of lead in semiconductor device |
| JPS6342416A (en) * | 1986-08-08 | 1988-02-23 | Hitoshi Ito | Haircut angle measuring instrument |
-
1986
- 1986-12-22 JP JP30370786A patent/JPS62169354A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5698853A (en) * | 1980-01-11 | 1981-08-08 | Hitachi Ltd | Structure of lead in semiconductor device |
| JPS6342416A (en) * | 1986-08-08 | 1988-02-23 | Hitoshi Ito | Haircut angle measuring instrument |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008166630A (en) * | 2006-12-29 | 2008-07-17 | Jst Mfg Co Ltd | Mounting member and its manufacturing method |
| JP2013051373A (en) * | 2011-08-31 | 2013-03-14 | Fujifilm Corp | Method for manufacturing electronic device |
| US20220157699A1 (en) * | 2019-03-18 | 2022-05-19 | Ampleon Netherlands B.V. | Electronic Molded Package |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0321096B2 (en) | 1991-03-20 |
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