JPS6342416B2 - - Google Patents
Info
- Publication number
- JPS6342416B2 JPS6342416B2 JP55001334A JP133480A JPS6342416B2 JP S6342416 B2 JPS6342416 B2 JP S6342416B2 JP 55001334 A JP55001334 A JP 55001334A JP 133480 A JP133480 A JP 133480A JP S6342416 B2 JPS6342416 B2 JP S6342416B2
- Authority
- JP
- Japan
- Prior art keywords
- solder
- lead
- tip
- leads
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 18
- 239000008188 pellet Substances 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 description 35
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000005219 brazing Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Description
【発明の詳細な説明】
本発明は半導体装置のリード構造に関し、特に
実装基板へのろう付を良好にしたリード構造に関
するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a lead structure for a semiconductor device, and particularly to a lead structure that can be easily brazed to a mounting board.
半導体装置を実装基板に実装する場合、近年で
は実装基板に形成した回路上にリードを接触させ
てこれを半田等によりろう付けする所謂片面塔載
による取付が行なわれている。これは、主にフラ
ツトパツケージ型の半導体装置に施されることが
多く、従来のデイアルインライン型の半導体のよ
うにリードを基板に貫通させてリード周囲をろう
付ける構造と比較して、実装スペース（厚さ寸
法）が低減でき、高密度の実装を可能にするとい
う利点がある。 When mounting a semiconductor device on a mounting board, in recent years, so-called single-sided mounting has been carried out, in which leads are brought into contact with circuits formed on the mounting board and then brazed with solder or the like. This is often applied to flat package type semiconductor devices, and compared to the structure of conventional daily-in-line type semiconductors, in which the leads penetrate the board and the area around the leads is brazed, it is It has the advantage of reducing space (thickness) and enabling high-density packaging.
このような片面塔載を行なうため、従来では第
１図に示すように、パツケージ１から突出された
リード２の先端２ａを実装基板３面と平行になる
ように略90゜折曲し、この先端部２ａを基板表面
に形成した回路上に乗せて、両者を半田４付けし
ている。この場合、通常では回路には半田印刷を
施しており、この半田を溶融させると同時にリー
ド先端部２ａを回路の半田４上に押圧することに
よつて半田付が行なわれるようになつている。 In order to carry out such single-sided mounting, conventionally, as shown in FIG. The tip 2a is placed on a circuit formed on the surface of the substrate, and both are soldered 4. In this case, the circuit is usually printed with solder, and soldering is carried out by melting the solder and simultaneously pressing the lead tip 2a onto the solder 4 of the circuit.
ところが、このリード先端部２ａの構造では、
先端部と回路との接触面積は大きくとれるもの
の、この接触面積の大きいことがかえつて逆に作
用して先端部２ａ上側面への半田の回り込みが抑
制され、接着性に充分満足できるものが得られな
いという問題が生じている。即ち、先端部２ａの
接触面積が大きいため、先端部２ａを溶融半田上
に押圧すると、半田は左右方向へ押しやられ同時
に半田には表面張力が作用して球面状になろうと
するため、押しやられた半田が先端部２ａの上面
にまで回り込んで接着することが困難になるため
である。 However, with the structure of this lead tip 2a,
Although the contact area between the tip and the circuit can be made large, this large contact area has the opposite effect and suppresses the solder from going around to the upper surface of the tip 2a, resulting in a fully satisfactory adhesion. The problem is that it cannot be done. That is, since the contact area of the tip 2a is large, when the tip 2a is pressed onto the molten solder, the solder is pushed in the left and right direction, and at the same time, surface tension acts on the solder and tries to take on a spherical shape, so it is pushed away. This is because the solder spreads to the upper surface of the tip portion 2a, making it difficult to bond it.
また、このように接触面積が大きいと、先端部
２ａと回路の半田４との接着面における半田の濡
れ性を外観から確認或いは検査することが難かし
いという問題もある。 Further, when the contact area is large as described above, there is also a problem that it is difficult to visually confirm or inspect the wettability of the solder on the adhesive surface between the tip portion 2a and the solder 4 of the circuit.
したがつて本発明の目的は半田等のろう材との
濡れ性が良好で回路との接着性がよく、しかも外
観からの濡れ性の検査が容易な半導体装置のリー
ド構造を提供することにある。 Therefore, an object of the present invention is to provide a lead structure for a semiconductor device that has good wettability with a brazing material such as solder, good adhesion to a circuit, and can be easily inspected for wettability from the outside. .
このような目的を達成するための本発明は、第
２図および第３図に図示した如く、半導体ペレツ
トを封止するパツケージと、そのパツケージより
外部に導出する所定幅をもつ複数のリードとを有
し、そしてそのリードの先端部は実装基板面に当
接し、ろう付けされる先端面をもつように構成さ
れてなる半導体装置であつて、そのリード先端部
のリード側面にはリード幅を狭くする如き傾斜面
をもち、かつその傾斜面はリード先端面に交わつ
ていることを特徴とする半導体装置にある。 To achieve such an object, the present invention, as shown in FIGS. 2 and 3, includes a package for sealing a semiconductor pellet, and a plurality of leads having a predetermined width led out from the package. The semiconductor device is configured to have a tip end surface that is brought into contact with the surface of the mounting board and is soldered to the surface of the mounting board. A semiconductor device is characterized in that the semiconductor device has an inclined surface as shown in FIG.
以下、本発明の実施例を図面に基づいて説明す
る。 Embodiments of the present invention will be described below based on the drawings.
第２図は本発明のリード構造を有するフラツト
パツケージ型半導体装置の要部斜視図であり、図
において、１１は半導体ペレツトやこの半導体と
リードとを接続するワイヤ等をレジンモールド等
にて封止したパツケージ、１２はこのパツケージ
１１内にインナーリードをモールドさせ、パツケ
ージ１１の四周側からアウターリード１３を突出
させた複数本のリードである。このリード１２は
パツケージ１１からは横方向に向つて突出されて
いるがすぐ下方に向つて略直角に折曲しており、
更に、このリード１２の先端部１４は実装基板１
５の実装面に形成した半田印刷回路１６の上面に
略垂直方向に当接するようになつている。前記リ
ード１２の先端部１４の形状は、第３図に合わせ
て示すように、先端部の中央部１７を幾分残して
その両側を削成し、先端面或いは両側面に対して
所定の角度θ0をもつた傾斜面１８として構成して
いる。そして、これら先端面中央部１７と傾斜面
１８には半田めつき等を行なつて表面に半田塗膜
を形成しているのである。 FIG. 2 is a perspective view of the main parts of a flat package type semiconductor device having a lead structure according to the present invention. In the figure, reference numeral 11 denotes a semiconductor pellet, a wire connecting the semiconductor and the lead, etc., sealed with a resin mold or the like. The stopped package 12 is a plurality of leads with inner leads molded inside the package 11 and outer leads 13 protruding from the four circumferential sides of the package 11. This lead 12 projects laterally from the package cage 11, but is bent immediately downward at a substantially right angle.
Furthermore, the tip portion 14 of this lead 12 is attached to the mounting board 1.
The solder printed circuit 16 is brought into contact with the upper surface of the solder printed circuit 16 formed on the mounting surface of No. 5 in a substantially perpendicular direction. As shown in FIG. 3, the shape of the tip 14 of the lead 12 is formed by cutting off both sides of the tip, leaving some of the center 17, and forming a predetermined angle with respect to the tip surface or both side surfaces. It is configured as an inclined surface 18 having an angle of θ 0 . The central portion 17 of the tip end face and the inclined surface 18 are soldered to form a solder coating on the surface.
以上の構成によれば、半導体装置の実装に際し
ては、第４図に示すように、加熱されて溶融状態
にある半田印刷回路１６上に略垂直方向にリード
１２先端を当接し、更にこれを仮想線のように押
込んでゆくと、それだけで印刷回路の半田１６は
リード１２の先端面中央部１７はもとより傾斜面
１８とも良好に濡れた状態となり、同図のように
両側の半田が盛り上るようにしてリード先端をろ
う付けするのである。したがつて、実装板１５へ
のリード１２のろう付けを強固に行ない得ると共
に、リード先端部は実装板に対して略垂直方向に
接続されているので接続状態の外観判断を比較的
容易に行なうことができる。 According to the above configuration, when mounting a semiconductor device, as shown in FIG. By pushing the wire in a straight line, the solder 16 of the printed circuit will become well wetted not only at the center 17 of the tip end surface of the lead 12 but also at the inclined surface 18, and the solder on both sides will swell up as shown in the figure. Then, the tip of the lead is brazed. Therefore, the leads 12 can be firmly brazed to the mounting board 15, and since the lead ends are connected in a direction substantially perpendicular to the mounting board, it is relatively easy to visually judge the connection state. be able to.
更に、リード先端面中央部１７と傾斜面１８に
は予め半田めつき等によつて半田塗膜を形成して
いるため、回路印刷の半田との濡れ性は更に向上
する。尚、リードの前後面１９，２０（第２図参
照）の先端部にも半田塗膜を形成しておけば、前
後面における濡れ性の向上にも有効である。 Further, since a solder coating film is previously formed on the center portion 17 of the lead end face and the inclined surface 18 by solder plating or the like, wettability with solder for circuit printing is further improved. Incidentally, if a solder coating is also formed on the tips of the front and rear surfaces 19 and 20 (see FIG. 2) of the leads, it is effective to improve the wettability of the front and rear surfaces.
ここで、前記リード１２の半田との濡れ性を考
察する。一般に半田は溶融状態で表面張力が大き
く、実装板上で球面状態になろうとする。この性
質はリード先端部が半田上に当接されかつ押込ま
れたときにも表われ、押込まれたリードの両側に
押分けられた半田も夫々表面張力により球面状態
になろうとする。このとき、第５図Ａ，Ｂに比較
図示するように、側面１８′が垂直のＡの状態で
は側面と半田１６′との接触性はあまり良好では
ないが、Ｂのように側面１８が傾斜していると側
面は半田１６の球面に近接して接触性は良好にな
る。したがつて、前記実施例における傾斜面１８
の傾斜角θ0は半田の接触角θ1に近似する値が好ま
しい。 Here, the wettability of the leads 12 with solder will be considered. Generally, solder has a large surface tension in its molten state and tends to form a spherical shape on the mounting board. This property also appears when the tip of the lead is brought into contact with the solder and pushed in, and the solder pushed out on both sides of the pushed lead also tends to form a spherical shape due to surface tension. At this time, as shown in FIGS. 5A and 5B for comparison, in the state A where the side surface 18' is vertical, the contact between the side surface and the solder 16' is not very good, but as shown in B, the side surface 18 is inclined. If this is done, the side surfaces will be close to the spherical surface of the solder 16 and the contact will be good. Therefore, the inclined surface 18 in the above embodiment
The inclination angle θ 0 is preferably a value that approximates the contact angle θ 1 of the solder.
また、リード先端部１４を半田に押込んでゆく
ときに、リード面と半田とを衝突させる方が接着
性は良好になることから、傾斜面１８を形成して
リードと半田との衝突面積を増大することも半田
との濡れを良好にする理由となつている。したが
つて、先端面中央部１７の面積と傾斜面１８の面
積（但し、半田の厚さを考慮した実質的な傾斜面
積）の和が最大となるようにこれらを定めればよ
く、実際上はリード全巾寸法に対する中央部の巾
寸法を約1/8若しくはこれよりも若干大きくすれ
ばよい。 In addition, when pushing the lead tip 14 into the solder, the adhesion is better if the lead surface collides with the solder, so the inclined surface 18 is formed to increase the collision area between the lead and the solder. This is also a reason for good wetting with solder. Therefore, it is sufficient to determine these so that the sum of the area of the center portion 17 of the tip surface and the area of the inclined surface 18 (however, the actual inclined area considering the thickness of the solder) is the maximum, and in practice, The width of the center portion of the lead should be approximately 1/8 or slightly larger than the entire width of the lead.
尚、第６図に示すように、傾斜面を規定する傾
斜角θXを順次変化させて、傾斜面を凹曲面１８Ａ
として形成してもよい。このようにすれば、凹曲
面１８Ａは半田の球面に沿うようになり、接着性
を一段と向上することができる。 Incidentally, as shown in FIG. 6, by sequentially changing the inclination angle θ
It may be formed as In this way, the concave curved surface 18A will follow the spherical surface of the solder, and the adhesiveness can be further improved.
以上の説明のように本発明のリード構造は、リ
ード先端部の両側に先端面に対して傾斜した傾斜
面を形成し、かつろう材の塗膜を形成しているの
で、構造が極めて簡単でありながらろう材との濡
れ性が向上して良好な接続構造を得ることができ
ると共に、接続状態の外観検査を容易に行なうこ
とができる等の効果を奏する。 As explained above, the lead structure of the present invention has an extremely simple structure because it has sloped surfaces on both sides of the lead tip that are inclined with respect to the tip surface, and a coating film of brazing material. However, the wettability with the brazing material is improved and a good connection structure can be obtained, and the appearance of the connection state can be easily inspected.
第１図は従来のリード構造の側面図、第２図は
本発明のリード構造を示す半導体装置の要部斜視
図、第３図はリード先端部の拡大正面図、第４図
はろう付状態を示す正面図、第５図Ａ，Ｂは濡れ
性を比較した模式的正面図、第６図は他の実施例
のリード先端部の拡大正面図である。
１１…半導体パツケージ、１２…リード、１４
…先端部、１５…実装基板、１６…回路印刷半
田、１７…先端面中央部、１８…傾斜面、１８Ａ
…凹曲面、θ0，QX…傾斜角、θ1…接触角。
Fig. 1 is a side view of a conventional lead structure, Fig. 2 is a perspective view of the main parts of a semiconductor device showing the lead structure of the present invention, Fig. 3 is an enlarged front view of the lead tip, and Fig. 4 is a brazed state. FIGS. 5A and 5B are schematic front views comparing wettability, and FIG. 6 is an enlarged front view of the lead tip of another example. 11...Semiconductor package, 12...Lead, 14
... Tip part, 15... Mounting board, 16... Circuit printed solder, 17... Center part of tip surface, 18... Inclined surface, 18A
...concave surface, θ 0 , Q X ... inclination angle, θ 1 ... contact angle.
Claims (1)
のパツケージより外部に導出する所定幅をもつ複
数のリードとを有し、そしてそのリードの先端部
は実装基板面に当接し、ろう付けされる先端面を
もつように構成されてなる半導体装置であつて、
そのリード先端部のリード側面にはリード幅を狭
くする如き傾斜面をもち、かつその傾斜面はリー
ド先端面に交わつていることを特徴とする半導体
装置。1 It has a package that seals a semiconductor pellet, and a plurality of leads having a predetermined width that lead out from the package, and the tips of the leads are in contact with the mounting board surface and the tip surface to be brazed is A semiconductor device configured to have
A semiconductor device characterized in that a lead side surface of the lead tip portion has an inclined surface that narrows the lead width, and the inclined surface intersects with the lead tip surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP133480A JPS5698853A (en) | 1980-01-11 | 1980-01-11 | Structure of lead in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP133480A JPS5698853A (en) | 1980-01-11 | 1980-01-11 | Structure of lead in semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30370786A Division JPS62169354A (en) | 1986-12-22 | 1986-12-22 | Packaging structure of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5698853A JPS5698853A (en) | 1981-08-08 |
| JPS6342416B2 true JPS6342416B2 (en) | 1988-08-23 |
Family
ID=11498593
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP133480A Granted JPS5698853A (en) | 1980-01-11 | 1980-01-11 | Structure of lead in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5698853A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01132148A (en) * | 1981-07-27 | 1989-05-24 | Texas Instr Inc <Ti> | Integrated circuit carrier |
| JPS59108389A (en) * | 1982-12-13 | 1984-06-22 | マルコン電子株式会社 | Method of producing hybrid integrated circuit |
| JPS6188471A (en) * | 1984-10-05 | 1986-05-06 | 松下電器産業株式会社 | Connector |
| JPH0510366Y2 (en) * | 1985-08-31 | 1993-03-15 | ||
| JPS62169354A (en) * | 1986-12-22 | 1987-07-25 | Hitachi Ltd | Packaging structure of semiconductor device |
| JPH051909Y2 (en) * | 1987-04-30 | 1993-01-19 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5279258A (en) * | 1975-12-25 | 1977-07-04 | Nippon Electric Co | Container for electronic circuit parts |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5756527Y2 (en) * | 1977-02-25 | 1982-12-04 |
-
1980
- 1980-01-11 JP JP133480A patent/JPS5698853A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5279258A (en) * | 1975-12-25 | 1977-07-04 | Nippon Electric Co | Container for electronic circuit parts |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5698853A (en) | 1981-08-08 |
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