JPH04171854A - Lead frame for semiconductor device - Google Patents
Lead frame for semiconductor deviceInfo
- Publication number
- JPH04171854A JPH04171854A JP2299523A JP29952390A JPH04171854A JP H04171854 A JPH04171854 A JP H04171854A JP 2299523 A JP2299523 A JP 2299523A JP 29952390 A JP29952390 A JP 29952390A JP H04171854 A JPH04171854 A JP H04171854A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- tip
- semiconductor device
- lead frame
- cut
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 238000000926 separation method Methods 0.000 claims abstract description 4
- 238000007747 plating Methods 0.000 abstract description 10
- 229910000679 solder Inorganic materials 0.000 abstract description 10
- 238000005476 soldering Methods 0.000 abstract description 8
- 230000005499 meniscus Effects 0.000 abstract description 5
- 238000005452 bending Methods 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 abstract description 2
- 238000009736 wetting Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 2
- 230000000694 effects Effects 0.000 description 3
- 229910000978 Pb alloy Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 235000014676 Phragmites communis Nutrition 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000011179 visual inspection Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置用リードフレームに関し、特に外部
リードの形状に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lead frame for a semiconductor device, and particularly to the shape of an external lead.
従来の半導体装置では、第３図（ａ）に示すように、放
射状に広がっている多数の外部リード３が、タイバ一部
２及びフレーム部１で互いに連結されており、その間は
凹部を有さないストレートな平面形状で構成されている
。第３図（ｂ）において、半導体素子１１は、アイラン
ド４に固着された後、樹脂封止によりパッケージ部５が
構成される。その後、外部リード３の半田付性を良好な
ものとする為に、この外部リード３に鉛又は錫Φ鉛合金
めっき７が施される。半導体装置は、その後タイバ一部
２が切断され、外部リート先端が第３図（ａ）の破線ａ
の位置で切断され、第３図（ｂ）の状態となり、そして
外部リード３は曲げ加工され、第３図（Ｃ）の状態とな
る。In a conventional semiconductor device, as shown in FIG. 3(a), a large number of external leads 3 extending radially are connected to each other by a tie bar part 2 and a frame part 1, and there is a recess between them. It is composed of a straight planar shape. In FIG. 3(b), after the semiconductor element 11 is fixed to the island 4, a package portion 5 is formed by resin sealing. Thereafter, in order to improve the solderability of the external leads 3, lead or tin/Φ-lead alloy plating 7 is applied to the external leads 3. In the semiconductor device, the tie bar portion 2 is then cut, and the external reed tip is aligned with the broken line a in FIG. 3(a).
The external lead 3 is cut at the position shown in FIG. 3(b), and the external lead 3 is bent to obtain the state shown in FIG. 3(c).
完成した半導体装置は、第３図（ｄ）に示すように、プ
リント基板１０に半田付実装される。The completed semiconductor device is soldered and mounted on a printed circuit board 10, as shown in FIG. 3(d).
切断分離した後の外部リード３の先端部８の切断面には
、外装めっき７が被覆していない。その為、半田付実装
後の半田メニスカス９は、第３図（ｄ）に示すように小
さく、リード先端部の半田付性が悪い。The cut surface of the tip end 8 of the external lead 3 after being cut and separated is not coated with the exterior plating 7. Therefore, the solder meniscus 9 after soldering and mounting is small as shown in FIG. 3(d), and the solderability of the lead tips is poor.
従来の半導体装置のリードフレームでは、外部リード３
の先端を形成するために切断分離を行った場合、切断面
には錫、或は錫Ｏ鉛合金の外装めっきが被覆していない
。In conventional semiconductor device lead frames, external leads 3
When cutting and separating is performed to form the tip of the cut surface, the cut surface is not coated with an exterior plating of tin or tin-O-lead alloy.
そのため、切断面の半田濡れが悪く、半田付強度が劣化
すると共に、半田付後の外観検査において、リード先端
方向から半田メニスカス９を認識することが難しく正確
な検査ができないという問題点があった。As a result, there was a problem in that solder wettability of the cut surface was poor, deteriorating the soldering strength, and in the visual inspection after soldering, it was difficult to recognize the solder meniscus 9 from the direction of the lead tip, making accurate inspection impossible. .
本発明の目的は、前記問題点を解決し、リード先端部の
半田付性が良好になるようにした半導体装置用リードフ
レームを提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a lead frame for a semiconductor device that solves the above-mentioned problems and has good solderability at the tip of the lead.
本発明の半導体装置用リードフレームの構成は、外部リ
ードの切断分離予定位置に、凹部を設けていることを特
徴とする。The structure of the lead frame for a semiconductor device of the present invention is characterized in that a recess is provided at a position where the external lead is to be cut and separated.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）は本発明の一実施例の半導体装置用リード
フレームの平面図である。FIG. 1(a) is a plan view of a lead frame for a semiconductor device according to an embodiment of the present invention.
第１図（ａ）において、本実施例のリードフレームは、
外部リード３の切断分離位置に、厚み方向の凹部を有す
る。外部リード３の切断分離位置を破線ａで示している
。第１図（ｂ）に示すように、凹部６が形成されており
、このほぼ中央線の破線ａで切断される。この切断の前
に、外装めっき７が両型面に施される。In FIG. 1(a), the lead frame of this example is
A recess in the thickness direction is provided at the position where the external lead 3 is cut and separated. The cutting and separation position of the external lead 3 is indicated by a broken line a. As shown in FIG. 1(b), a recessed portion 6 is formed and is cut along a broken line a approximately at the center of the recessed portion 6. Before this cutting, exterior plating 7 is applied to both mold surfaces.
第１図（Ｃ）に示すように、封入後、外装めっき７を施
した半導体装置の断面図である。第１図（ｄ）に示すよ
うに、リードの曲げ工程を経た後の半導体装置を、基板
１０に半田付実装した場合が示されている。外装めっき
７は、外部リード３の凹部６にも被覆されている為、半
田メニスカス９が広がり、半田濡れが良くなっており、
半田付強度も向上する。As shown in FIG. 1(C), this is a cross-sectional view of the semiconductor device to which exterior plating 7 has been applied after encapsulation. As shown in FIG. 1(d), the semiconductor device after the lead bending step is soldered and mounted on the substrate 10. Since the exterior plating 7 also covers the concave portion 6 of the external lead 3, the solder meniscus 9 spreads, improving solder wetting.
Soldering strength is also improved.
以上、第３図（ａ）乃至第３図（ｄ）と、本実施例とが
同様の部分については、説明を割愛した。In the above, descriptions of parts that are similar between FIGS. 3(a) to 3(d) and this embodiment have been omitted.
続いて、本発明の他の実施例について説明する。Next, other embodiments of the present invention will be described.
第２図（ａ）は、本発明の他の実施例のリードフレーム
の平面図である。第２図（ａ）において、本実施例は、
リードフレームの外部リード３の切断分離予定位置に幅
方向の凹部６′を有する。この場合、外部リード３は破
線ａの位置で切断分離がなされ、その形状は第２図（ｂ
）の様になる。第２図（ｂ）のＢ１−８２線の断面を、
第２図（Ｃ）に示す。本実施例のＩＪ −）’先端部８
には、外装めっき７は施されていないが、凹部６の先端
部８−ａにはめっきが施されており、前記一実施例と同
様の効果を有する。FIG. 2(a) is a plan view of a lead frame according to another embodiment of the present invention. In FIG. 2(a), in this example,
A recess 6' in the width direction is provided at a position where the external lead 3 of the lead frame is to be cut and separated. In this case, the external lead 3 is cut and separated at the position indicated by the broken line a, and its shape is shown in FIG.
). The cross section taken along the B1-82 line in Figure 2(b) is
It is shown in FIG. 2(C). IJ-)' tip part 8 of this example
, the outer plating 7 is not applied, but the tip 8-a of the recess 6 is plated, and has the same effect as the previous embodiment.
以上説明したように、本発明は、リードフレームの外部
リードを形成するために切断分離を行う位置に、凹部を
設けたことによって、リード先端の半田濡れ性が良くな
り、半田付強度が向上するという効果を有する。As explained above, the present invention provides recesses at the positions where the external leads of the lead frame are cut and separated, thereby improving the solder wettability of the lead tips and improving the soldering strength. It has this effect.
第１図（ａ）は本発明の一実施例の半導体装置用リード
フレームを示す平面図、第１図（ｂ）は第１図（ａ）の
凹部のある外部リードの断面図、第１図（Ｃ）は第１図
（ｂ）の外部リードをめっきし、切断した状態を示す断
面図、第１図（ｄ）は第１図（Ｃ）の外部リードを基板
に半田付けした状態を示す断面図、第２図（ａ）は本発
明の他の実施例のリードフレームを示す平面図、第２図
（ｂ）は第２図（ａ）のリードフレームを切断後の状態
を示す斜視図、第２図（Ｃ）は第２図（ｂ）のＢ１−Ｂ
２線に沿って切断して見た断面図、第３図（ａ）は従来
のリードフレームを示す平面図、第３図（ｂ）乃至第３
図（ｄ）は従来の半導体装置用リードフレームを用いて
、半導体装置を製造し、実装する状態を順に示した断面
図である。
１・・・フレーム部、２・・・タイバ一部、３・・・外
部リード、４・・・アイランド、５・・・樹脂封止部、
６゜６′・・・凹部、７・・・外装めっき、８＋８ａ・
・・外部リード先端、９・・・半田メニスカス、１０・
・・プリント基板。FIG. 1(a) is a plan view showing a lead frame for a semiconductor device according to an embodiment of the present invention, FIG. 1(b) is a sectional view of an external lead with a recessed portion shown in FIG. 1(a), (C) is a sectional view showing the state in which the external lead in Fig. 1(b) has been plated and cut, and Fig. 1(d) shows the state in which the external lead in Fig. 1(C) has been soldered to the board. 2(a) is a plan view showing a lead frame according to another embodiment of the present invention, and FIG. 2(b) is a perspective view showing the state after cutting the lead frame of FIG. 2(a). , FIG. 2(C) is B1-B in FIG. 2(b)
3(a) is a plan view showing a conventional lead frame, and FIGS. 3(b) to 3.
Figure (d) is a cross-sectional view sequentially showing the state in which a semiconductor device is manufactured and mounted using a conventional lead frame for a semiconductor device. DESCRIPTION OF SYMBOLS 1... Frame part, 2... Part of tie bar, 3... External lead, 4... Island, 5... Resin sealing part,
6゜6'...Concavity, 7...Exterior plating, 8+8a・
...External lead tip, 9...Solder meniscus, 10.
··Printed board.
Claims (1)
定位置に、凹部を設けたことを特徴とする半導体装置用
リードフレーム。A lead frame for a semiconductor device, characterized in that a recess is provided at a position where cutting and separation is planned to form the tip of an external lead of the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2299523A JP2583353B2 (en) | 1990-11-05 | 1990-11-05 | Lead frame for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2299523A JP2583353B2 (en) | 1990-11-05 | 1990-11-05 | Lead frame for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04171854A true JPH04171854A (en) | 1992-06-19 |
| JP2583353B2 JP2583353B2 (en) | 1997-02-19 |
Family
ID=17873697
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2299523A Expired - Fee Related JP2583353B2 (en) | 1990-11-05 | 1990-11-05 | Lead frame for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2583353B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH065767A (en) * | 1992-06-23 | 1994-01-14 | Nec Kyushu Ltd | Lead frame for semiconductor device |
| WO2004036647A1 (en) * | 2002-10-17 | 2004-04-29 | Rohm Co.,Ltd. | Method for cutting lead terminal of package type electronic component |
| EP2852002A1 (en) * | 2013-09-20 | 2015-03-25 | Dai-Ichi Seiko Co., Ltd. | Electric part soldered onto printed circuit board |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63127168U (en) * | 1987-02-12 | 1988-08-19 | ||
| JPH03104148A (en) * | 1989-09-18 | 1991-05-01 | Mitsubishi Electric Corp | Package for semiconductor integrated circuit |
-
1990
- 1990-11-05 JP JP2299523A patent/JP2583353B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63127168U (en) * | 1987-02-12 | 1988-08-19 | ||
| JPH03104148A (en) * | 1989-09-18 | 1991-05-01 | Mitsubishi Electric Corp | Package for semiconductor integrated circuit |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH065767A (en) * | 1992-06-23 | 1994-01-14 | Nec Kyushu Ltd | Lead frame for semiconductor device |
| WO2004036647A1 (en) * | 2002-10-17 | 2004-04-29 | Rohm Co.,Ltd. | Method for cutting lead terminal of package type electronic component |
| US7364947B2 (en) | 2002-10-17 | 2008-04-29 | Rohm Co., Ltd. | Method for cutting lead terminal of package type electronic component |
| EP2852002A1 (en) * | 2013-09-20 | 2015-03-25 | Dai-Ichi Seiko Co., Ltd. | Electric part soldered onto printed circuit board |
| US9668347B2 (en) | 2013-09-20 | 2017-05-30 | Dai-Ichi Seiko Co., Ltd. | Electric part soldered onto printed circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2583353B2 (en) | 1997-02-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |