JPH05326788A - Lead frame material and semiconductor device provided therewith - Google Patents

Lead frame material and semiconductor device provided therewith

Info

Publication number
JPH05326788A
JPH05326788A JP4132717A JP13271792A JPH05326788A JP H05326788 A JPH05326788 A JP H05326788A JP 4132717 A JP4132717 A JP 4132717A JP 13271792 A JP13271792 A JP 13271792A JP H05326788 A JPH05326788 A JP H05326788A
Authority
JP
Japan
Prior art keywords
lead
lead frame
thin
inner lead
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4132717A
Other languages
Japanese (ja)
Inventor
Susumu Okikawa
進 沖川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Nippon Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Steel Corp filed Critical Nippon Steel Corp
Priority to JP4132717A priority Critical patent/JPH05326788A/en
Publication of JPH05326788A publication Critical patent/JPH05326788A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To enable a lead frame provided with many pins fine in pitch to be easily formed, to keep the tip of the lead large enough in bonding width, and to form an outer lead thick enough to protect it against deformation by a method wherein the tip of the inner lead of the lead frame is formed thin- walled. CONSTITUTION:A predetermined lead frame forming spot is positioned on the surface of a material basing on an etching pattern, and a thin-walled recess 2 is provided to the inner lead of the lead frame or at least the tip of the inner lead. The recess 2 is formed by pressing with a die provided with a recess forming projection. By this setup, the thin-walled part 3 formed by pressure is reduced at least to 1/6 in thickness. In succession, an etching pattern of photoresist is formed on the surface of the inner lead including the recess 2, and an etching process is carried out. Thus, a lead frame 9 composed of an outer lead 7 as thick as usual, an inner lead 8 2/3 or below as thick as the outer lead 7, and a die pad 4 can be obtained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は特殊加工したインナーリ
ード用素材及びこの素材を利用した半導体装置に関する
ものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a specially processed inner lead material and a semiconductor device using this material.

【0002】[0002]

【従来の技術】半導体素子に形成される集積回路は、年
を追うごとに高集積、高機能化されており、これに伴っ
て接続回路も著しい多ピン構造となっている。この多ピ
ン構造にするために必然的に要求されるのが、リードフ
レームのファインピッチ化である。
2. Description of the Related Art An integrated circuit formed on a semiconductor element has been highly integrated and highly functionalized year by year, and accordingly, a connection circuit has a remarkably multi-pin structure. What is inevitably required to achieve this multi-pin structure is the fine pitch of the lead frame.

【0003】従来、リードフレームを加工する方法に
は、マスキングした素材を腐食液中でエッチングしてリ
ード等を成形するエッチング法、或いはプレス打抜きで
成形するプレス加工法がある。プレス加工法は比較的簡
易にリードフレームを成形できるが、多ピン化傾向に対
応して数百オーダーのリードを加工するのは困難とされ
ている。一方、エチィング法ではプレス加工法に較べて
加工工数が多くコストも高いが、比較的高精度のファイ
ンピッチ化が可能となる。
Conventionally, as a method of processing a lead frame, there is an etching method in which a masked material is etched in a corrosive solution to form a lead or the like, or a press processing method in which a lead is formed by press punching. Although the press working method can relatively easily form a lead frame, it is difficult to process a lead of several hundred orders in response to the tendency of increasing the number of pins. On the other hand, the etching method requires a large number of processing steps and is high in cost as compared with the press processing method, but it is possible to achieve a fine pitch with relatively high accuracy.

【0004】通常、リードフレームをファインピッチ化
する場合に、リード幅の限界は板厚の7〜8割程度とい
われている。従って、更にファインピッチ化するために
リード幅を狭くするには板厚を薄くする必要がある。し
かし、板厚を薄くすることは強度不足を招くことにな
り、ハンドリングや接合等においてリードが曲ったり、
折れたりする不都合が起りやすい。
It is generally said that when the lead frame is made finer, the lead width is limited to about 70 to 80% of the plate thickness. Therefore, it is necessary to reduce the plate thickness in order to reduce the lead width in order to achieve a finer pitch. However, reducing the plate thickness leads to insufficient strength, bending of the lead during handling and joining,
Inconvenience such as breaking easily occurs.

【0005】また、従来のリードフレーム素材は厚さが
均等であるが、エッチングでリードフレームを制作する
際に均一に腐食されない場合があり、特に幅が狭くなる
リードフレーム先端部分は、その断面を図8に示すよう
に腐食が局部的に進行し、均一な断面にならないことが
ある。従って、強度低下を生じることがあると共に特に
表面部にも腐食が及ぶと接合面積が不足し、ワイヤボン
ディングが不可能となることがある。
Although the conventional lead frame material has a uniform thickness, it may not be uniformly corroded when the lead frame is produced by etching. As shown in FIG. 8, corrosion may locally progress and a uniform cross section may not be obtained. Therefore, the strength may be reduced, and particularly when the surface portion is also corroded, the bonding area becomes insufficient, and wire bonding may become impossible.

【0006】[0006]

【発明が解決しようとする課題】このように、現状では
多ピン化に伴うリード先端幅とピッチの加工は限界に入
っているといえる。本発明は上記したような現状の問題
点を解消するものであって、リードフレームの先端部分
(インナーリード部分)を薄肉にし、リード成形後にお
ける断面形状が均一になると共に一層の多ピン構造に適
合し得るリードフレーム素材、及び該素材を加工して制
作したリードフレームを用いる半導体装置を提供するこ
とを目的とするものである。
As described above, at present, it can be said that the processing of the lead tip width and the pitch due to the increase in the number of pins has reached the limit. SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems of the present situation by making the leading end portion (inner lead portion) of the lead frame thin so that the cross-sectional shape after lead molding becomes uniform and a more multi-pin structure is formed. An object of the present invention is to provide a compatible lead frame material and a semiconductor device using a lead frame manufactured by processing the material.

【0007】[0007]

【課題を解決するための手段】上記目的を達成するため
に本発明は以下の構成を要旨とする。すなわち、 (1)製品厚さにしたリードフレーム素材板に、あらかじ
め定めたリードフレーム採寸ピッチ内で、リードフレー
ムの少なくともインナーリード先端となる部分を薄肉化
したことを特徴とするとするリードフレーム素材。 (2)前記インナーリード先端となる部分を、プレス加工
で薄肉凹部に形成してなることを特徴とするリードフレ
ーム素材。 (3)前記リードフレームの少なくともインナーリード先
端となる部分を素材より除去し、この除去した部分に薄
肉板を接合したことを特徴とするとするリードフレーム
素材。 (4)前各項のリードフレーム素材をエッチング、プレス
等公知の手段で薄肉インナーリード部を有するリードフ
レームに成形し、ダイパッドに搭載した半導体素子と、
前記薄肉インナーリードを細線で連結した構成体を樹脂
封止したことを特徴とする半導体装置である。
In order to achieve the above object, the present invention has the following structures. That is, (1) a lead frame material characterized in that a lead frame material plate having a product thickness has a thinned portion at least the inner lead tips of the lead frame within a predetermined lead frame measuring pitch. (2) A lead frame material characterized in that a portion which becomes the tip of the inner lead is formed into a thin recess by press working. (3) A lead frame material, characterized in that at least a portion of the lead frame, which will be the tip of the inner lead, is removed from the material, and a thin plate is joined to the removed portion. (4) A semiconductor element mounted on a die pad by molding the lead frame material of the preceding items into a lead frame having a thin inner lead portion by a known means such as etching and pressing,
A semiconductor device is characterized in that a structure in which the thin inner leads are connected by a thin wire is resin-sealed.

【0008】以下に本発明を詳細に説明する。図1は本
発明のリードフレーム素材1の一例を示す。この素材は
従来使用されている42Ni合金或いはCu等からなる
合金や金属であり、圧延で製造された板(帯)から切り
出されたものである。素材の厚さは種々あるが、現状で
多ピン限界とされる厚さは100〜150μmであり、
本発明はこの様な素材をベースにしても、現状以上の一
層の多ピン化傾向に対応できる。
The present invention will be described in detail below. FIG. 1 shows an example of a lead frame material 1 of the present invention. This material is a conventionally used 42Ni alloy or an alloy or metal composed of Cu or the like, which is cut out from a plate (band) manufactured by rolling. Although there are various thicknesses of materials, the thickness that is currently considered as a multi-pin limit is 100 to 150 μm,
The present invention is capable of coping with the tendency toward higher pin counts than the current situation, even if such materials are used as a base.

【0009】本発明は上記した材質の素材1から、リー
ドフレームを従来より行われているエッチング法を用い
て採取するのであるが、それに先立って、エッチングパ
ターンに基づき、素材表面に予め定めたリードフレーム
採取位置決めをし、そのリード先端部分、即ちインナー
リード部分或いは最小限インナーリードの先端となる部
分に、薄肉化した凹部2(2a〜2n)を形成する。採
取すべきリードフレームの一例をB部(点線)に示し
た。
According to the present invention, the lead frame is sampled from the raw material 1 of the above-mentioned material by the conventional etching method. Prior to that, the lead frame previously determined on the raw material surface based on the etching pattern is taken. The frame is sampled and positioned, and thinned recesses 2 (2a to 2n) are formed in the lead tip portion, that is, the inner lead portion or at least the tip of the inner lead. An example of the lead frame to be sampled is shown in part B (dotted line).

【0010】凹部2の形成は、凹部2成形用の凸部を有
する押型(図示せず)でプレスする方法を採用すること
が好ましい。これにより圧下成形される薄肉部3は元の
厚さより最低でも1/6は減厚される。減厚度合はピン
数や材質によっても異なるが、あまり薄くするとハンド
リング等に不便を来すので元の厚さの2/3を超えない
ようにすることが望ましい。しかもこの様な減厚部分は
プレスにより強度が上昇する。図2に図1のA−A線断
面、即ち凹部2断面の一例を拡大して示しているよう
に、インナーリード及びパッド部分を凹部としている。
凹部2はこの様な断面形状に限らず、例えば図3に示す
ように半導体素子を載置するダイパッド4部分は圧下を
せず、インナーリードとなる部分のみに圧下を加えて凹
部2を形成してもよい。凹部2の裏側にはプレスにより
材料が突出することもあるが、この場合はグラインダー
等によって除去すればよい。
The depression 2 is preferably formed by pressing with a pressing die (not shown) having a projection for molding the depression 2. As a result, the thickness of the thin-walled portion 3 formed by the reduction is reduced to at least 1/6 of the original thickness. Although the degree of reduction in thickness depends on the number of pins and the material, if it is too thin, it will be inconvenient for handling, so it is desirable not to exceed 2/3 of the original thickness. Moreover, the strength of such a reduced thickness portion is increased by pressing. As shown in FIG. 2 by enlarging an example of a cross section taken along the line AA of FIG. 1, that is, a cross section of the recess 2, the inner lead and the pad portion are recesses.
The recess 2 is not limited to such a cross-sectional shape. For example, as shown in FIG. 3, the die pad 4 portion on which the semiconductor element is mounted is not pressed down, and the recess 2 is formed only by applying the pressure to the portion to be the inner lead. May be. The material may be projected on the back side of the recess 2 by pressing, but in this case, it may be removed by a grinder or the like.

【0011】また、凹部2の形成方法は上記に限らず、
例えば図4に示すように、先ずインナーリードとなる部
分を打抜き、この打抜いた部分に別の薄肉部材5をロウ
付け、溶接等の公知の接合手段で一体的に強固に接続6
する方法を採用できる。
The method of forming the recess 2 is not limited to the above,
For example, as shown in FIG. 4, first, an inner lead portion is punched, another thin member 5 is brazed to the punched portion, and firmly connected integrally by a known joining means such as welding 6
Can be adopted.

【0012】この様に凹部2を形成した素材は、その凹
部を含む表面にホトレジストでエッチングパターンを形
成し、公知の手段でエッチングを行うことにより、図5
に断面パターンを示すように、通常の肉厚を持つアウタ
ーリード部7とアウターリード部7のほぼ2/3以下の
厚さを有するインナーリード8及びダイパッド4からな
るリードフレーム9を得ることができる。また、この際
得られる薄肉インナーリード8は、図6に示すように表
面が浸蝕されることなく所定のボンディングエリヤを確
保する巾(min.90μm)を有し、かつ表裏がほぼ等し
い均一な断面形状となっている。
The material in which the recesses 2 are formed in this way is formed by forming an etching pattern with a photoresist on the surface including the recesses and performing etching by a known means.
As shown in the cross-sectional pattern, a lead frame 9 including an outer lead portion 7 having a normal wall thickness, an inner lead 8 having a thickness of approximately 2/3 or less of the outer lead portion 7 and a die pad 4 can be obtained. .. In addition, the thin inner lead 8 obtained at this time has a width (min. 90 μm) that secures a predetermined bonding area without eroding the surface as shown in FIG. It has a shape.

【0013】図7は上記した素材より得られたリードフ
レーム9を使用した半導体装置である。即ち、薄肉化さ
れたパッド4には半導体素子10をAgペーストで接合
し、同様に薄肉化されたインナーリード8にはAgメッ
キ11を施して電極を設け、前記半導体素子10と電極
11とをAu細線12で接合した構成体を、樹脂封止1
3して半導体装置を構成している。図中14はプリント
基盤である。
FIG. 7 shows a semiconductor device using a lead frame 9 obtained from the above materials. That is, the semiconductor element 10 is bonded to the thinned pad 4 with an Ag paste, and the similarly thinned inner lead 8 is plated with Ag to provide an electrode, and the semiconductor element 10 and the electrode 11 are connected to each other. The structure bonded with the Au thin wire 12 is sealed with resin 1
3 to form a semiconductor device. Reference numeral 14 in the drawing is a print substrate.

【0014】上記装置において、薄肉化されたインナー
リード8は従来製品に見られるような不均一さは無く、
強度も低下しておらず、むしろ組織的に強化されている
ため、ハンドリングやワイヤ接合時は勿論のこと、樹脂
封止等の実装時にもトラブルの発生はなかった。
In the above apparatus, the thinned inner lead 8 does not have the unevenness as seen in the conventional products,
Since the strength was not reduced and the structure was rather strengthened, no trouble occurred not only during handling and wire joining but also during mounting such as resin sealing.

【0015】[0015]

【発明の効果】以上のように本発明は、インナーリード
部分の板厚を薄くしたため現状の限界を打ち破るファイ
ンピッチの多ピンリードフレームの制作が容易にでき、
しかもリード先端に所定のボンディング幅を確保でき
る。また、パッド部分をも薄肉成形することにより薄型
パッケージとすることができると共にアウターリードは
従来通りに厚く成形できるのでリード変形に対しても十
分に耐えらる。このように本発明は、ますます多ピン化
する趨勢に合致する極めて有用な半導体装置を提供で来
る。
As described above, according to the present invention, since the plate thickness of the inner lead portion is made thin, it is possible to easily manufacture a fine pitch multi-pin lead frame that breaks the current limit.
Moreover, a predetermined bonding width can be secured at the tip of the lead. In addition, since the pad portion can also be thinly molded to form a thin package and the outer lead can be thickly formed as in the conventional case, it is sufficiently resistant to lead deformation. As described above, the present invention provides a very useful semiconductor device that meets the trend of increasing the number of pins.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明リードフレーム素材の一態様を示す斜視
図。
FIG. 1 is a perspective view showing one embodiment of a lead frame material of the present invention.

【図2】図1のA−A線断面図。FIG. 2 is a sectional view taken along line AA of FIG.

【図3】本発明素材の他の凹部を示す断面図FIG. 3 is a sectional view showing another concave portion of the material of the present invention.

【図4】本発明素材凹部の別の実施態様を示す断面図。FIG. 4 is a cross-sectional view showing another embodiment of the material recessed portion of the present invention.

【図5】本発明におけるリードフレームの態様を示す断
面説明図。
FIG. 5 is an explanatory cross-sectional view showing an aspect of a lead frame in the present invention.

【図6】本発明の薄肉リード部の断面図。FIG. 6 is a sectional view of the thin lead portion of the present invention.

【図7】本発明の半導体装置の一例を示す断面説明図。FIG. 7 is a cross-sectional explanatory view showing an example of a semiconductor device of the present invention.

【図8】従来のリード部の一例を示す断面説明図。FIG. 8 is a cross-sectional explanatory view showing an example of a conventional lead portion.

【符号の説明】[Explanation of symbols]

1:素材 2:凹部 3:薄肉部材 4:ダイパッド 5:別の薄肉部材 6:接合部 7:アウターリード 8:インナーリード 9:リードフレーム 10:半導体素子 11:Agメッキ 12:Au細線 13:樹脂封止 14:プリント基盤 1: Material 2: Recessed part 3: Thin-walled member 4: Die pad 5: Another thin-walled member 6: Joined part 7: Outer lead 8: Inner lead 9: Lead frame 10: Semiconductor element 11: Ag plating 12: Au thin wire 13: Resin Sealing 14: Printed board

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 製品厚さにしたリードフレーム素材板
に、あらかじめ定めたリードフレーム採寸ピッチ内で、
リードフレームの少なくともインナーリード先端となる
部分を薄肉化したことを特徴とするとするリードフレー
ム素材。
1. A lead frame material plate having a product thickness, within a predetermined lead frame measuring pitch,
A lead frame material characterized in that at least a portion of the lead frame, which is the tip of the inner lead, is thinned.
【請求項2】 プレス加工で薄肉凹部を形成してなるこ
とを特徴とするとする請求項1記載のリードフレーム素
材。
2. The lead frame material according to claim 1, wherein the thin recess is formed by press working.
【請求項3】 リードフレームの少なくともインナーリ
ード先端となる部分を素材より除去し、この除去した部
分に薄肉板を接合したことを特徴とするとする請求項1
記載のリードフレーム素材。
3. A lead frame, at least a portion which becomes an inner lead tip is removed from a raw material, and a thin plate is joined to the removed portion.
Lead frame material described.
【請求項4】 請求項1のリードフレーム素材をエッチ
ング、プレス等公知の手段で薄肉インナーリード部を有
するリードフレームに成形し、ダイパッドに搭載した半
導体素子と、前記薄肉インナーリードを細線で連結した
構成体を樹脂封止したことを特徴とする半導体装置。
4. The lead frame material according to claim 1 is molded into a lead frame having a thin inner lead portion by a known means such as etching or pressing, and a semiconductor element mounted on a die pad and the thin inner lead are connected by a thin wire. A semiconductor device in which a structure is resin-sealed.
JP4132717A 1992-05-25 1992-05-25 Lead frame material and semiconductor device provided therewith Withdrawn JPH05326788A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4132717A JPH05326788A (en) 1992-05-25 1992-05-25 Lead frame material and semiconductor device provided therewith

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4132717A JPH05326788A (en) 1992-05-25 1992-05-25 Lead frame material and semiconductor device provided therewith

Publications (1)

Publication Number Publication Date
JPH05326788A true JPH05326788A (en) 1993-12-10

Family

ID=15087935

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4132717A Withdrawn JPH05326788A (en) 1992-05-25 1992-05-25 Lead frame material and semiconductor device provided therewith

Country Status (1)

Country Link
JP (1) JPH05326788A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000349219A (en) * 1999-06-03 2000-12-15 Mitsubishi Electric Corp Lead-out terminal, case for the same and power semiconductor device
US6501156B1 (en) 1999-09-10 2002-12-31 Matsushita Electric Industrial Co., Ltd. Lead frame which includes a die pad, a support lead, and inner leads
US7102216B1 (en) * 2001-08-17 2006-09-05 Amkor Technology, Inc. Semiconductor package and leadframe with horizontal leads spaced in the vertical direction and method of making
JP2008034830A (en) * 2006-06-27 2008-02-14 Seiko Instruments Inc Semiconductor device, and lead frame and its manufacturing method
JP2017028333A (en) * 1999-06-30 2017-02-02 ルネサスエレクトロニクス株式会社 Semiconductor device manufacturing method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000349219A (en) * 1999-06-03 2000-12-15 Mitsubishi Electric Corp Lead-out terminal, case for the same and power semiconductor device
JP2017028333A (en) * 1999-06-30 2017-02-02 ルネサスエレクトロニクス株式会社 Semiconductor device manufacturing method
US6501156B1 (en) 1999-09-10 2002-12-31 Matsushita Electric Industrial Co., Ltd. Lead frame which includes a die pad, a support lead, and inner leads
US7102216B1 (en) * 2001-08-17 2006-09-05 Amkor Technology, Inc. Semiconductor package and leadframe with horizontal leads spaced in the vertical direction and method of making
JP2008034830A (en) * 2006-06-27 2008-02-14 Seiko Instruments Inc Semiconductor device, and lead frame and its manufacturing method

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