JP2509882B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2509882B2 JP2509882B2 JP33787494A JP33787494A JP2509882B2 JP 2509882 B2 JP2509882 B2 JP 2509882B2 JP 33787494 A JP33787494 A JP 33787494A JP 33787494 A JP33787494 A JP 33787494A JP 2509882 B2 JP2509882 B2 JP 2509882B2
- Authority
- JP
- Japan
- Prior art keywords
- finger
- connecting portion
- gold
- substrate
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は、IC,LSI等の半導
体チップを固定するリードフレームに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame for fixing semiconductor chips such as IC and LSI.
【0002】[0002]
【従来の技術】従来より半導体チップを樹脂モールドで
一体化して複数ピンを突設した半導体装置の組立てには
金属製のリードフレームが用いられている。このリード
フレームは薄い銅箔状金属板をプレスで撃ち抜いたり、
エッチングなどによって形成されており、その形状は図
11に示すように、半導体チップ1を取り付ける矩形の
タブ2をその4隅において支持するタブリードと、タブ
2の周縁に内端を臨ませる複数のフィンガ4と、これら
フィンガ4及びタブリード3の外端を支持する枠部5
と、枠部5の両端縁に沿って定間隔に設けられたスプロ
ケット孔6とからなっている。2. Description of the Related Art Heretofore, a metal lead frame has been used for assembling a semiconductor device in which a semiconductor chip is integrated with a resin mold and a plurality of pins are projected. This lead frame is a thin copper foil metal plate punched with a press,
As shown in FIG. 11, the tab leads are formed by etching or the like and support rectangular tabs 2 to which the semiconductor chip 1 is attached at their four corners, and a plurality of fingers whose inner ends are exposed to the peripheral edges of the tabs 2. 4 and a frame portion 5 that supports the outer ends of the fingers 4 and the tab leads 3.
And sprocket holes 6 provided at regular intervals along both edges of the frame portion 5.
【0003】このようなリードフレーム7を用いて半導
体装置を組立てるには、まずタブ2上に半導体チップ1
を取り付けた後、半導体チップ1の各電極とこれに対応
するフィンガ4の内端をワイヤあるいはワイヤを用いず
直接に接続し、その後矩形枠部5の内側領域を合成樹脂
でモールドし半導体チップ1を被覆し、次いで枠部5を
切除して半導体装置を得るのである。In order to assemble a semiconductor device using such a lead frame 7, the semiconductor chip 1 is first mounted on the tab 2.
After mounting, the electrodes of the semiconductor chip 1 and the inner ends of the fingers 4 corresponding to the electrodes are directly connected without using wires or wires, and then the inner region of the rectangular frame portion 5 is molded with synthetic resin to form the semiconductor chip 1 Then, the frame portion 5 is cut off to obtain a semiconductor device.
【0004】[0004]
【発明が解決しようとする課題】ところで、リードフレ
ーム7のフィンガ4の先端は図12に示すように半導体
チップ1の電極1aに半田その他の手段を用いて接続さ
れるのであるが、一般に電極1aはシリコン1b上に薄
膜状に形成されたアルミニウムパッドからなり、周囲の
保護膜1cより凹んだ位置にある。By the way, the tip of the finger 4 of the lead frame 7 is connected to the electrode 1a of the semiconductor chip 1 by soldering or other means as shown in FIG. Is an aluminum pad formed in a thin film on the silicon 1b and is located at a position recessed from the surrounding protective film 1c.
【0005】そこでフィンガ4の先端部には電極1aと
接続を容易にするためバンプのような接続部4aが形成
されるのであるが、フィンガ4及び接続部4aが銅箔状
金属板で形成されている場合、電極1aとの接続が不完
全なものとなる傾向にあり、このため接続部4a全体を
金で形成すれば接続は容易かつ確実になる反面、金素材
の使用量が増加し高価になることが予測される。Therefore, a connecting portion 4a such as a bump is formed at the tip of the finger 4 to facilitate connection with the electrode 1a. The finger 4 and the connecting portion 4a are formed of a copper foil metal plate. In this case, the connection with the electrode 1a tends to be incomplete. Therefore, if the entire connection portion 4a is made of gold, the connection is easy and reliable, but the amount of gold material used increases and the cost is high. Is expected to become.
【0006】このために、接続部に金メッキをすること
により金の効率的使用が提案されているが、例えば特開
昭47−27675号公報に記載のものは、リードフレ
ーム素材に、予め部分的金メッキクラフドを施し、これ
をプレス加工してリードフレームを得るものであるが、
プレス精度を考慮してボンディングする先端部の金クラ
ッドは所望のリード幅よりも広目に施されることにな
り、金の無駄が生じるものである。For this reason, it has been proposed to use gold efficiently by plating the connecting portion with gold. For example, the one disclosed in Japanese Patent Laid-Open No. 47275/1972 discloses a lead frame material which is partially pre-formed. The lead frame is obtained by applying gold-plated craft and pressing this.
The gold clad at the tip end for bonding in consideration of pressing accuracy is made wider than the desired lead width, resulting in waste of gold.
【0007】また特開昭55−6862号公報に記載の
ものはエッチングによりインナーリードを形成し、その
表面に金メッキを施したものであるが、インナーリード
全体をメッキするため、金の効率的使用にはやはり無駄
があるものである。The one disclosed in Japanese Patent Laid-Open No. 55-6862 has an inner lead formed by etching, and the surface of the inner lead is plated with gold. Since the entire inner lead is plated, efficient use of gold is possible. After all, there is waste.
【0008】[0008]
【課題を解決するための手段】本発明は上記点に鑑みて
なされたもので、フィンガ(4)に、半導体チップ
(1)の電極と接続するバンプ状接続部(4a)を配
し、該接続部(4a)の上記接続面側を金,すず,半田
等の接触材(12)で被覆してなる半導体装置の製造方
法において、フィンガ(4)に相当する部分が露出する
ようレジスト層(9)を設けた電鋳用基板(8)の、上
記接続部(4a)に相当する部分に、予め上記接触材
(12)を施し、その上面にフィンガ(4)を電鋳形成
し、その後、前記基板(8)を剥離してなるものであ
る。The present invention has been made in view of the above points, and a bump-shaped connecting portion (4a) connected to an electrode of a semiconductor chip (1) is arranged on a finger (4), In a method of manufacturing a semiconductor device in which the connection surface side of the connection portion (4a) is covered with a contact material (12) such as gold, tin, or solder, a resist layer (so as to expose a portion corresponding to the finger (4)). The contact material (12) is preliminarily applied to a portion of the electroforming substrate (8) provided with 9) corresponding to the connecting portion (4a), and the finger (4) is electroformed on the upper surface thereof. The substrate (8) is peeled off.
【0009】[0009]
【作用】このような半導体装置の製造方法によれば、例
えば銅箔状フィンガとアルミニウム電極との接合は、従
来と同じ金−アルミ合金となり、接続強度が従来より劣
化することがなく、無垢状金バンプを形成しないので、
製造コストを低減することができる。According to such a method of manufacturing a semiconductor device, for example, a copper foil finger and an aluminum electrode are joined to each other by using the same gold-aluminum alloy as in the conventional case, and the connection strength is not deteriorated as compared with the conventional case. Since it does not form gold bumps,
The manufacturing cost can be reduced.
【0010】しかも、接続部の接触材は、面精度の高い
基板に直接形成されるため、基板から剥離された接触材
面つまり半導体チップの電極と接続される面は精度の高
いものとなり、接続信頼性の高いものが得られる。Moreover, since the contact material of the connecting portion is directly formed on the substrate having high surface accuracy, the surface of the contact material separated from the substrate, that is, the surface connected to the electrode of the semiconductor chip has high accuracy, and the connection is made. Highly reliable product can be obtained.
【0011】[0011]
【実施例】図1ないし図4は本発明の実施例におけるリ
ードフレームの成形工程を示す図である。まず図1の如
くステンレス等の導電性金属からなる基板8上に所望パ
ターンのレジスト層9を形成する。このレジスト層9は
リードフレーム7を形成しない位置にのみ積層されるも
のであって、非レジスト部分の形状は所望パターンのリ
ードフレーム形状である。1 to 4 are views showing a molding process of a lead frame in an embodiment of the present invention. First, as shown in FIG. 1, a resist layer 9 having a desired pattern is formed on a substrate 8 made of a conductive metal such as stainless steel. The resist layer 9 is laminated only on the position where the lead frame 7 is not formed, and the shape of the non-resist portion is the lead frame shape of the desired pattern.
【0012】次にこの基板8上に、レジストがアルカリ
現像タイプではカセイソーダを、溶剤タイプの場合は塩
化メチレン等の溶剤を用いて剥離処理を行う。その後こ
の基板8の非レジスト部分上に塗布または電鋳により
金,すず,半田等の接触材12を施す。その後、この上
面に銅,ニッケル等の金属を電鋳により積層して金属層
10を形成する。Next, a peeling process is performed on the substrate 8 by using caustic soda when the resist is an alkali developing type and by using a solvent such as methylene chloride when the resist is a solvent type. After that, a contact material 12 such as gold, tin, or solder is applied to the non-resist portion of the substrate 8 by coating or electroforming. Then, a metal such as copper or nickel is laminated on the upper surface by electroforming to form the metal layer 10.
【0013】次に図2に示すように積層体全体にプレス
加工を施し、基板8を突出するようにフィンガ相当部分
を折り曲げる。折り曲げ形状はフィンガ基部4b、連結
部4c、先端部4dから構成されるものであるが、先端
部4dの下面には同様にバンプのような接続部4aをプ
レスにより形成する。Next, as shown in FIG. 2, the entire laminated body is subjected to press working, and the portions corresponding to the fingers are bent so that the substrate 8 is projected. The bent shape is composed of a finger base portion 4b, a connecting portion 4c, and a tip portion 4d. Similarly, a connection portion 4a such as a bump is formed by pressing on the lower surface of the tip portion 4d.
【0014】次いで金属層10上に第二次の電鋳加工を
施し、図3の如き銅,ニッケル等の第2の金属層11を
金属層10上に形成する。この電鋳加工においては、平
坦なフィンガ基部4b、先端部4dに対して連結部4c
は傾斜した位置にあるため、電鋳による金属層11は連
結部4cではその成長速度が遅い。Next, a second electroforming process is performed on the metal layer 10 to form a second metal layer 11 of copper, nickel or the like on the metal layer 10 as shown in FIG. In this electroforming process, the flat finger base 4b and the flat tip 4d are connected to the connecting portion 4c.
Since the metal layer 11 is inclined, the growth rate of the electroformed metal layer 11 is slow in the connecting portion 4c.
【0015】また、フィンガ4の先端部4dは細い頸部
によって連結部4cに連結されているため、電流密度が
大きくなり、金属はこの部分でより成長する。従って、
図からもわかるように連結部4cの肉厚はフィンガ基部
4bの肉厚より小さく最小で、先端部4dの肉厚は最大
となる。Further, since the tip portion 4d of the finger 4 is connected to the connecting portion 4c by the thin neck portion, the current density is increased and the metal grows more in this portion. Therefore,
As can be seen from the figure, the wall thickness of the connecting portion 4c is smaller than the wall thickness of the finger base portion 4b and is minimum, and the wall thickness of the tip portion 4d is maximum.
【0016】最後に基板8を剥離すれば図4の如き形状
のフィンガ4を有するリードフレーム7が得られる。特
にこの場合には、フィンガ4の半導体チップと接合する
側が、基板8のプレス形状及び寸法そのままとなるた
め、プレス精度に応じてフィンガ4の精度を向上させる
ことができ、より一層多ピン化に対応できる。Finally, the substrate 8 is peeled off to obtain the lead frame 7 having the fingers 4 having the shape as shown in FIG. Particularly, in this case, the side of the finger 4 to be joined with the semiconductor chip remains the press shape and size of the substrate 8, so that the accuracy of the finger 4 can be improved according to the press accuracy, and the number of pins can be further increased. Can handle.
【0017】また、レジスト層9を形成しただけの基板
8をまず所望形状にプレス加工し、次いで接触材12を
施し、その後一次電鋳、もしくは一次電鋳と二次電鋳を
し、基板8からこの電鋳による金属層を剥離してそのま
まリードフレームとすることも可能である。The substrate 8 on which the resist layer 9 has just been formed is first pressed into a desired shape, then the contact material 12 is applied, and then primary electroforming or primary electroforming and secondary electroforming is performed to obtain the substrate 8. It is also possible to peel off the metal layer formed by electroforming to obtain a lead frame as it is.
【0018】このように上記実施例では、フィンガを含
むリードフレームは基本的に電鋳によって形成されるか
ら、プレス成形によって打ち抜き成形するのが困難な多
数フィンガをもつリードフレームであっても、エッチン
グ等の不安定な製造方法を用いることなく容易に成形す
ることができるとともに、フィンガ先端のバンプ及びバ
ンプを支持する可撓性を有する連結部を第二次の電鋳に
より同時にかつ容易に成形することができるものであ
る。As described above, in the above-described embodiment, since the lead frame including the fingers is basically formed by electroforming, even a lead frame having a large number of fingers which is difficult to punch by press molding is etched. Can be easily formed without using an unstable manufacturing method such as the above, and at the same time, the bumps at the finger tips and the flexible connecting portions supporting the bumps can be simultaneously and easily formed by secondary electroforming. Is something that can be done.
【0019】このようなフィンガを配したリードフレー
ム7を用いて半導体チップ1と接続する際には、まずリ
ードフレーム7のフィンガ先端のバンプ状接続部4aを
電極1aに対向するよう位置合わせを行い、次いで接続
部4aの背面側からボンディングツールで加熱加圧し金
−アルミニウム合金が形成され接続する。この加圧時、
この加圧力は接続部4aを加圧方向に押し曲げ変形する
よう作用し、この力がフィンガ基部1まで伝達し影響を
与えようとするが、接続部4aとフィンガ基部4bとの
間に連結部4cを配し、この連結部4cがフィンガ基部
4bより大きな可撓性を発揮するため、上記加圧力は柔
軟な連結部4cで緩和され、フィンガ基部4bへの影響
を軽減できる。これは相対的に、半導体チップ1側をフ
ィンガ4側へ押圧加工する場合でも同様である。なおバ
ンプ部分の接合された部分の周囲は金等で被覆されてい
るので、酸化防止が図られる。When connecting to the semiconductor chip 1 using the lead frame 7 having such fingers, first, the bump-shaped connecting portions 4a at the tips of the fingers of the lead frame 7 are aligned so as to face the electrodes 1a. Then, a gold-aluminum alloy is formed by heating and pressurizing with a bonding tool from the back surface side of the connecting portion 4a to connect. During this pressurization
This pressing force acts so as to push and deform the connecting portion 4a in the pressurizing direction, and this force is transmitted to the finger base portion 1 to exert an influence, but the connecting portion between the connecting portion 4a and the finger base portion 4b is affected. 4c is arranged, and the connecting portion 4c exerts greater flexibility than the finger base portion 4b. Therefore, the pressing force is relieved by the flexible connecting portion 4c, and the influence on the finger base portion 4b can be reduced. This is relatively the same even when the semiconductor chip 1 side is pressed to the finger 4 side. Since the periphery of the joined portion of the bump portion is covered with gold or the like, oxidation can be prevented.
【0020】したがって、接続部4aと電極1aとの接
合に傾きが発生しても、この接続部4aに続く連結部4
cがこの傾きを吸収し、フィンガ基部(一般に接続部よ
りも幅広くなっているが)までもが傾きあるいは、横ず
れを発生し隣接するフィンガとのピッチが乱れることも
なく、接続作業を容易にすることができる。Therefore, even if the joint between the connecting portion 4a and the electrode 1a is tilted, the connecting portion 4 following the connecting portion 4a is formed.
c absorbs this inclination, and even the finger base portion (which is generally wider than the connection portion) is not inclined or lateral shift occurs and the pitch with adjacent fingers is not disturbed, and the connection work is facilitated. be able to.
【0021】[0021]
【発明の効果】以上のように本発明によれば、フィンガ
(4)に、半導体チップ(1)の電極と接続するバンプ
状接続部(4a)を配し、該接続部(4a)の上記接続
面側を金,すず,半田等の接触材(12)で被覆してな
る半導体装置の製造方法において、フィンガ(4)に相
当する部分が露出するようレジスト層(9)を設けた電
鋳用基板(8)の、上記接続部(4a)に相当する部分
に、予め上記接触材(12)を施し、その上面にフィン
ガ(4)を電鋳形成し、その後、前記基板(8)を剥離
してなるので、半導体チップの電極1aとフィンガ先端
の接続部4aとの接続が確実に行なわれ、また接続部4
aは過剰に酸化することなく保護でき、しかもこれらの
ための金素材等の高価な接触材12の使用量を削減で
き、コストを低下させることができる。As described above, according to the present invention, bump-shaped connecting portions (4a) connected to the electrodes of the semiconductor chip (1) are arranged on the fingers (4), and the above-mentioned connecting portions (4a) are connected. In a method of manufacturing a semiconductor device in which a contact surface side is covered with a contact material (12) such as gold, tin, solder, etc., electroforming in which a resist layer (9) is provided so that a portion corresponding to a finger (4) is exposed. The contact material (12) is previously applied to a portion of the substrate (8) corresponding to the connection portion (4a), and the finger (4) is electroformed on the upper surface thereof, and then the substrate (8) is attached. Since it is peeled off, the connection between the electrode 1a of the semiconductor chip and the connection portion 4a at the tip of the finger is surely performed, and the connection portion 4 is also formed.
a can be protected without being excessively oxidized, and the amount of the expensive contact material 12 such as a gold material used for them can be reduced, and the cost can be reduced.
【0022】特に接触材12は、基板8上に最初に形成
されるため、その精度は、基板8の精度そのままに再現
されるため、信頼性の高い接続が可能である。In particular, since the contact material 12 is first formed on the substrate 8, the accuracy thereof is reproduced as it is, so that highly reliable connection is possible.
【図1】本発明の実施例におけるリードフレームの製造
工程の説明図で金属層形成工程である。FIG. 1 is an explanatory diagram of a lead frame manufacturing process in an example of the present invention, which is a metal layer forming process.
【図2】同製造工程の折曲加工工程である。FIG. 2 is a bending process of the manufacturing process.
【図3】同製造工程の第2金属形成工程である。FIG. 3 is a second metal forming step of the manufacturing process.
【図4】同製造工程により得られたリードフレームであ
る。FIG. 4 is a lead frame obtained by the same manufacturing process.
【図5】本発明を用いる一般的なリードフレームの平面
図である。FIG. 5 is a plan view of a general lead frame using the present invention.
【図6】フィンガ先端のバンプと半導体チップの電極と
の関係を示す断面図である。FIG. 6 is a cross-sectional view showing the relationship between bumps at the tips of fingers and electrodes of a semiconductor chip.
1 半導体チップ 1a 電極 4 フィンガ 4a 接続部 8 基板 9 レジスト層 1 semiconductor chip 1a electrode 4 finger 4a connection part 8 substrate 9 resist layer
Claims (1)
の電極と接続するバンプ状接続部(4a)を配し、該接
続部(4a)の上記接続面側を金,すず,半田等の接触
材(12)で被覆してなる半導体装置の製造方法におい
て、 フィンガ(4)に相当する部分が露出するようレジスト
層(9)を設けた電鋳用基板(8)の、 上記接続部(4a)に相当する部分に、予め上記接触材
(12)を施し、 その上面にフィンガ(4)を電鋳形成し、 その後、前記基板(8)を剥離してなる半導体装置の製
造方法。1. A semiconductor chip (1) is attached to a finger (4).
A method for manufacturing a semiconductor device in which a bump-shaped connecting portion (4a) for connecting to the electrode is provided, and the connecting surface side of the connecting portion (4a) is covered with a contact material (12) such as gold, tin, or solder. In the above, in the electroforming substrate (8) provided with a resist layer (9) so that a portion corresponding to the finger (4) is exposed, a portion corresponding to the connecting portion (4a) is previously attached to the contact material (12). And a finger (4) is electroformed on its upper surface, and then the substrate (8) is peeled off.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33787494A JP2509882B2 (en) | 1994-12-26 | 1994-12-26 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33787494A JP2509882B2 (en) | 1994-12-26 | 1994-12-26 | Method for manufacturing semiconductor device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4146513A Division JPH0817220B2 (en) | 1992-05-11 | 1992-05-11 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH07211837A JPH07211837A (en) | 1995-08-11 |
JP2509882B2 true JP2509882B2 (en) | 1996-06-26 |
Family
ID=18312809
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP33787494A Expired - Lifetime JP2509882B2 (en) | 1994-12-26 | 1994-12-26 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2509882B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5548059B2 (en) * | 2010-07-22 | 2014-07-16 | トッパン・フォームズ株式会社 | Circuit element |
-
1994
- 1994-12-26 JP JP33787494A patent/JP2509882B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH07211837A (en) | 1995-08-11 |
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