JPH0722191B2 - Method for manufacturing lead frame of semiconductor device - Google Patents
Method for manufacturing lead frame of semiconductor deviceInfo
- Publication number
- JPH0722191B2 JPH0722191B2 JP60074299A JP7429985A JPH0722191B2 JP H0722191 B2 JPH0722191 B2 JP H0722191B2 JP 60074299 A JP60074299 A JP 60074299A JP 7429985 A JP7429985 A JP 7429985A JP H0722191 B2 JPH0722191 B2 JP H0722191B2
- Authority
- JP
- Japan
- Prior art keywords
- finger
- lead frame
- substrate
- tip
- electroforming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000000034 method Methods 0.000 title description 8
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 20
- 238000005323 electroforming Methods 0.000 claims description 15
- 238000000465 moulding Methods 0.000 claims description 4
- 239000002585 base Substances 0.000 description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- YMWUJEATGCHHMB-UHFFFAOYSA-N Dichloromethane Chemical compound ClCCl YMWUJEATGCHHMB-UHFFFAOYSA-N 0.000 description 3
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000011121 sodium hydroxide Nutrition 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49534—Multi-layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔技術分野〕 本発明はIC、LSI等の半導体チツプを固定するのに用い
るリードフレームの製造方法に関する。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a lead frame used for fixing a semiconductor chip such as an IC or an LSI.
従来より半導体チツプを樹脂モールドで一体化して複数
ピンを突設した半導体装置の組立てには金属製のリード
フレームが用いられている。このリードフレームは薄い
金属板をプレスで打ち抜いたり、エツチングなどによつ
て形成されており、その形状は第３図に示すように、半
導体チツプ１を取り付ける矩形のタブ２をその４隅にお
いて支持するタブリード３と、タブ２の周縁に内端を臨
ませる複数のフインガ４と、これらフインガ４及びタブ
リード３の外端を支持する枠部５と、枠部５の両側縁に
沿つて定間隔に設けられたスプロケツト孔６とからなつ
ている。2. Description of the Related Art Conventionally, a metal lead frame has been used for assembling a semiconductor device in which a semiconductor chip is integrated with a resin mold and a plurality of pins are projected. This lead frame is formed by punching a thin metal plate with a press or by etching, etc., and its shape supports rectangular tabs 2 for mounting the semiconductor chip 1 at its four corners, as shown in FIG. The tab leads 3, a plurality of fingers 4 having inner ends facing the periphery of the tabs 2, a frame 5 supporting the fingers 4 and outer ends of the tab leads 3, and provided at regular intervals along both side edges of the frame 5. And the sprocket holes 6 formed therein.
このようなリードフレーム７を用いて半導体装置を組立
てるには、まずタブ２上に半導体チツプ１を取り付けた
後、半導体チツプ１の各電極とこれに対応するフインガ
４の内端をワイヤあるいはワイヤを用いず直接に接続
し、その後矩形枠部５の内側領域を合成樹脂でモールド
し半導体チツプ１を被覆し、次いで枠部５を切除して半
導体装置を得るのである。In order to assemble a semiconductor device using such a lead frame 7, first, the semiconductor chip 1 is mounted on the tab 2, and then each electrode of the semiconductor chip 1 and the inner end of the finger 4 corresponding thereto is attached with a wire or a wire. The semiconductor chip is obtained by directly connecting without using it, then molding the inner region of the rectangular frame 5 with a synthetic resin to cover the semiconductor chip 1, and then cutting the frame 5.
ところで、リードフレーム７のフインガ４の先端は第４
図に示すように半導体チツプ１の電極1aに半田その他の
手段を用いて接続されるのであるが、一般に電極1aはシ
リコン1b上に薄膜状に形成されたアルミニウムパツドか
らなり、周囲の保護膜1cより凹んだ位置にある。そこで
フインガ４の先端部には電極1aと接続を容易にするため
バンプ4aが形成されるのであるが、近年において多数ピ
ンの半導体装置が望まれてくると、フインガ数は同様に
増加し、フインガ４の幅も極めて細いものとなるため、
上記バンプの形成が困難となつてきている。By the way, the tip of the finger 4 of the lead frame 7 is
As shown in the figure, it is connected to the electrode 1a of the semiconductor chip 1 by soldering or other means. Generally, the electrode 1a is made of an aluminum pad formed in a thin film on the silicon 1b, and the surrounding protective film. It is in a position recessed from 1c. Therefore, a bump 4a is formed at the tip of the finger 4 in order to facilitate connection with the electrode 1a. However, when a semiconductor device having a large number of pins has been desired in recent years, the number of fingers similarly increases, and Since the width of 4 is also extremely thin,
It is becoming difficult to form the bumps.
本発明は上記の点に鑑みてなされたもので、多数のバン
プ付フインガを備えたリードフレームを容易に成形でき
るリードフレームの製造方法の提供を目的としている。The present invention has been made in view of the above points, and an object of the present invention is to provide a method of manufacturing a lead frame that can easily form a lead frame having a large number of fingers with bumps.
上記目的を達成するための手段として、本発明は、半導
体チツプの電極と接続されるフインガを導電性金属薄板
にて形成したリードフレームの製造方法であつて、少な
くとも表面に導電性を有する基板に所望パターンのレジ
スト層を形成する工程と、レジスト層が形成されていな
い基板の表面に一次電鋳によりフインガを形成する工程
と、この基板をプレス成形して、フインガ基部の先方に
起立部を介してフインガ基部と略平行な先端部を形成す
る工程と、このプレス成形の後に二次電鋳により前記フ
インガ上に金属層を積層する工程と、一次電鋳ならびに
二次電鋳により形成されたリードフレームを基板より剥
離する工程とからなり、電鋳されたリードフレームを基
板より除去した状態そのままで、フインガ先端にバンプ
形状が得られるようにしたことを特徴としている。As a means for achieving the above object, the present invention is a method for producing a lead frame in which a finger connected to an electrode of a semiconductor chip is formed of a conductive metal thin plate, and at least a surface of the substrate having conductivity. A step of forming a resist layer of a desired pattern, a step of forming a finger on the surface of the substrate on which the resist layer is not formed by primary electroforming, and press-molding this substrate, through a standing part in front of the finger base. Forming a tip portion substantially parallel to the finger base, a step of laminating a metal layer on the finger by secondary electroforming after this press forming, and leads formed by primary electroforming and secondary electroforming The process consists of peeling the frame from the substrate, and the bump shape can be obtained at the tip of the finger without removing the electroformed lead frame from the substrate. It is characterized in the thing.
第１図は本発明の実施例におけるリードフレームの成形
工程を示す図である。FIG. 1 is a diagram showing a molding process of a lead frame in an embodiment of the present invention.
まず第１図（ａ）の如くステンレス等の導電性金属から
なる基板８上に所望パターンのレジスト層９を形成す
る。このレジスト層９はリードフレーム７を形成しない
位置にのみ積層されるものであつて、非レジスト部8aの
形状は所望パターンのリードフレーム形状である。First, as shown in FIG. 1A, a resist layer 9 having a desired pattern is formed on a substrate 8 made of a conductive metal such as stainless steel. The resist layer 9 is laminated only on the position where the lead frame 7 is not formed, and the shape of the non-resist portion 8a is a lead frame shape of a desired pattern.
次にこの基板８上に、レジストがアルカリ現像タイプで
はカセイソーダを、溶剤タイプの場合は塩化メチレン等
の溶剤を用いて剥離処理を行う。その後この基板８上に
電鋳により銅、ニツケル、金等の金属を積層させる。こ
れにより（ｂ）図の如くレジスト層９を除く非レジスト
部8a上にのみ金属層10が形状される。Next, a peeling process is performed on the substrate 8 by using caustic soda when the resist is an alkali developing type and by using a solvent such as methylene chloride when the resist is a solvent type. Then, a metal such as copper, nickel, or gold is laminated on the substrate 8 by electroforming. As a result, the metal layer 10 is formed only on the non-resist portion 8a excluding the resist layer 9 as shown in FIG.
このようにして一枚の板状に成形された基板８及び金属
層の積層体の一部をプレス成形により（ｃ）図の如く、
金属層側に突出するように折曲加工する。この成形部分
はリードフレーム７の中央部に位置するタブ２及びフイ
ンガ４先端部であつて、（ｃ）図ではタブ２に向かつて
対向して延出する一対のフインガ４を示しており、フイ
ンガ４は平坦なフインガ基部4b、基部4bより上方へ延び
る起立部4c、及び起立部4cから基部4bと略平行に延びる
先端部4dとをそれぞれ備えている。なおタブ２は特に必
要としない。A part of the laminated body of the substrate 8 and the metal layer thus formed into a single plate is press-formed as shown in FIG.
Bend so as to project to the metal layer side. This molded portion is the tip of the tab 2 and the finger 4 located in the center of the lead frame 7, and in FIG. 7 (c), a pair of fingers 4 extending toward and facing the tab 2 are shown. Reference numeral 4 includes a flat finger base portion 4b, an upright portion 4c extending upward from the base portion 4b, and a tip portion 4d extending from the upright portion 4c substantially parallel to the base portion 4b. The tab 2 is not particularly necessary.
次いで、上記の如く変形された積層体の金属層10上に再
び電鋳を施し、（ｄ）図の如き銅、ニツケル等の第２の
金属層11を積層する。この電鋳加工においては、平坦な
基部4b、先端部4dに対して起立部4cは傾斜した位置にあ
るため、電鋳による金属層11は起立部4cではその成長速
度が遅い。また、フインガ４の先端部4dは細い頸部によ
つて起立部4cに連結されているため、電流密度が大きく
なり、金属はこの部分でより成長する。従つて、図から
もわかるように起立部4cの肉厚t2は基部4bの肉厚t1より
小さく最小で、先端部4dの肉厚t3は最大（t3＞t1＞t2）
となる。Next, electroforming is performed again on the metal layer 10 of the laminated body deformed as described above, and the second metal layer 11 of copper, nickel, etc. as shown in FIG. In this electroforming process, since the upright portions 4c are inclined with respect to the flat base portion 4b and the front end portion 4d, the growth rate of the electroformed metal layer 11 is slow in the upright portions 4c. Further, since the tip end portion 4d of the finger 4 is connected to the standing portion 4c by the thin neck portion, the current density is increased, and the metal grows more in this portion. Therefore, as can be seen from the figure, the wall thickness t 2 of the rising portion 4c is smaller than the wall thickness t 1 of the base portion 4b and is the minimum, and the wall thickness t 3 of the tip portion 4d is the maximum (t 3 > t 1 > t 2 ).
Becomes
更に（ｅ）図に示すように、フインガ４の先端部4dには
金、すず、半田の如き材料からなる接点材12が塗布され
る。この接点材12は半導体チツプ１の電極1aとの接続を
より良好にするためのもので、特に必要としないがレジ
スト層13により他の部分を被覆した状態でフインガ４の
先端部4d上面に塗布もしくはメツキを施せばよい。Further, as shown in (e), a contact material 12 made of a material such as gold, tin, or solder is applied to the tip 4d of the finger 4. This contact material 12 is for improving the connection with the electrode 1a of the semiconductor chip 1, and although not particularly necessary, it is applied to the upper surface of the tip 4d of the finger 4 while the other portion is covered with the resist layer 13. Alternatively, you can apply a beard.
最後に積層体から基板８のみを剥離すれば、（ｆ）図に
示す如きフインガ４をもつリードフレーム７が得られ
る。得られたフインガ４の先端部4dはその突出方向に厚
みをもつバンプ4aを構成し、薄肉の起立部4cによつて適
度な可撓性を与えられることになる。Finally, by peeling only the substrate 8 from the laminated body, the lead frame 7 having the fingers 4 as shown in FIG. The tip portion 4d of the obtained finger 4 constitutes a bump 4a having a thickness in the projecting direction, and the thin upright portion 4c provides appropriate flexibility.
特に起立部4cの肉厚t2を小さくすることにより、半導体
チツプとの接合時の加工力を緩和させて基部4bの変形、
横ずれを防止することができ、この部分をバツフア領域
として使用できる。In particular, by reducing the wall thickness t 2 of the upright portion 4c, the processing force at the time of joining with the semiconductor chip is relaxed to deform the base portion 4b,
Lateral displacement can be prevented, and this portion can be used as a buffer area.
このバツフア領域は、先端部４を作るときのプレス加工
によつて同時に得られるので、特別な加工を必要とせ
ず、加工の簡素化が図れる。This buffer region can be obtained at the same time by press working when making the tip portion 4, so that no special working is required and the working can be simplified.
第２図は本発明の変形例を示す製造工程説明図である。FIG. 2 is a manufacturing process explanatory view showing a modified example of the invention.
即ち、（ａ）図に示すように、まずはじめに基板８上に
レジスト層９を形成した状態で第一次の電鋳加工を行う
点は第１図の実施例と同様である。但し、基板８の非レ
ジスト部8a上には予め金、すず、半田等の接触材12を塗
布もしくはメツキを施しておく。That is, as shown in FIG. 1A, the first electroforming process is performed in the state where the resist layer 9 is formed on the substrate 8 first, as in the embodiment shown in FIG. However, a contact material 12 such as gold, tin or solder is applied or plated on the non-resist portion 8a of the substrate 8 in advance.
次に（ｂ）図に示すように積層体全体にプレス加工を施
し、基板８を突出するようにフインガ相当部分を折り曲
げる。折り曲げ形状は第１図の実施例と同様に基部4b、
起立部4c、先端部4dから構成されるものであるが、先端
部4dの下面には同時にバンプ4aをプレスにより形成す
る。Next, as shown in FIG. 2B, the entire laminated body is subjected to press working, and the portion corresponding to the finger is bent so that the substrate 8 is projected. The bent shape is the same as in the embodiment of FIG.
The upright portion 4c and the tip 4d are formed, and the bump 4a is simultaneously formed on the lower surface of the tip 4d by pressing.
次いで金属層10上に第二次の電鋳加工を施し、（ｃ）図
の如き第２の金属層11を金属層10上に形成する。この際
前述したように先端部4d、基部4b、起立部4cの順でその
肉厚は大きく形成される。Then, a second electroforming process is performed on the metal layer 10 to form a second metal layer 11 on the metal layer 10 as shown in FIG. At this time, as described above, the front end portion 4d, the base portion 4b, and the standing portion 4c are formed in the order of increasing thickness.
最後に基板８を剥離すれば（ｄ）図の如き形状のフイン
ガ４を有するリードフレーム７が得られる。Finally, when the substrate 8 is peeled off, the lead frame 7 having the fingers 4 having the shape as shown in FIG.
特にこの場合には、フインガ４の、半導体チツプと接合
する側が、基板８のプレス形状及び寸法そのままとなる
ため、プレス精度に応じてフインガ４の精度を向上させ
ることができ、より一層多ピン化に対応できる。Particularly in this case, the side of the finger 4 to be joined to the semiconductor chip remains the press shape and size of the substrate 8, so that the accuracy of the finger 4 can be improved according to the press accuracy, and the number of pins is further increased. Can handle.
本発明は以上のように、平板の状態で一次電鋳してフイ
ンガを形成し、その後プレス成形してフインガ基部の先
方に起立部を介してフインガ基部と略平行な突出した先
端部を形成して、その後に二次電鋳により前記フインガ
上に金属層を積層している。As described above, the present invention forms a finger by primary electroforming in a flat plate state, and then press-molds the tip of the finger base to form a protruding tip portion substantially parallel to the finger base portion through an upright portion. Then, a metal layer is laminated on the finger by secondary electroforming.
そのため、フインガの先端部の肉厚を厚くすることがで
き、半導体チップの電極との接続が容易かつ確実とな
る。Therefore, the thickness of the tip portion of the finger can be increased, and the connection with the electrode of the semiconductor chip becomes easy and reliable.
一方、起立部の肉厚は特別な加工を施さずに必然的に薄
く抑えられ、この部分がバッファ領域として機能し、半
導体チップとの接合時の加圧力が緩和でき、フインガ基
部の変形、横ずれが防止できるなどの特長を有してい
る。On the other hand, the wall thickness of the upright part is inevitably reduced without any special processing, and this part functions as a buffer region, which can relieve the pressing force at the time of joining with the semiconductor chip, and the deformation and lateral displacement of the finger base can occur. It has the feature that it can prevent
第１図は本発明の実施例におけるリードフレームの製造
工程を説明する図、第２図は本発明の他の実施例におけ
るリードフレームの製造工程を説明する図、第３図は本
発明を用いる一般的なリードフレームの平面図、第４図
はフインガ先端のバンプと半導体チツプの電極との関係
を示す断面図である。 １…半導体チツプ、1a…電極、２…タブ、４…フイン
ガ、4a…バンプ、4b…フインガ基部、4c…起立部、4d…
フインガ先端部、７…リードフレーム、８…基板、8a…
非レジスト部、９…レジスト層、10…金属層、11…金属
層。FIG. 1 is a diagram for explaining a lead frame manufacturing process in an embodiment of the present invention, FIG. 2 is a diagram for explaining a lead frame manufacturing process in another embodiment of the present invention, and FIG. 3 is for using the present invention. FIG. 4 is a plan view of a general lead frame, and FIG. 4 is a cross-sectional view showing the relationship between the bumps at the tips of the fingers and the electrodes of the semiconductor chip. DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip, 1a ... Electrode, 2 ... Tab, 4 ... Finger, 4a ... Bump, 4b ... Finger base, 4c ... Standing part, 4d ...
Finger tip, 7 ... Lead frame, 8 ... Substrate, 8a ...
Non-resist part, 9 ... Resist layer, 10 ... Metal layer, 11 ... Metal layer.
フロントページの続き (72)発明者 坂田 栄二 福岡県田川郡方城町大字伊方4680番地 九 州日立マクセル株式会社内 (56)参考文献 特開 昭57−171681（ＪＰ，Ａ) 特開 昭55−110051（ＪＰ，Ａ) 特開 昭54−62128（ＪＰ，Ａ)Front page continuation (72) Eiji Sakata Eiji Sakata 4680 Ikata, Hachijo-machi, Tagawa-gun, Fukuoka Prefecture Kyushu Hitachi Maxell Co., Ltd. (56) References JP-A-57-171681 (JP, A) JP-A-55- 110051 (JP, A) JP-A-54-62128 (JP, A)
Claims (1)
を導電性金属薄板にて形成したリードフレームの製造方
法であつて、 少なくとも表面に導電性を有する基板に所望パターンの
レジスト層を形成する工程と、 レジスト層が形成されていない基板の表面に一次電鋳に
よりフインガを形成する工程と、 この基板をプレス成形して、フインガ基部の先方に起立
部を介してフインガ基部と略平行な先端部を形成する工
程と、 このプレス成形の後に二次電鋳により前記フインガ上に
金属層を積層する工程と、 一次電鋳ならびに二次電鋳により形成されたリードフレ
ームを基板より剥離する工程とからなる半導体装置のリ
ードフレーム製造方法。1. A method of manufacturing a lead frame in which a finger connected to an electrode of a semiconductor chip is formed of a conductive metal thin plate, wherein a resist layer having a desired pattern is formed on at least a surface of a conductive substrate. And a step of forming a finger on the surface of the substrate on which the resist layer is not formed by primary electroforming, and press-molding this substrate to the tip of the finger base, which is substantially parallel to the finger base through the standing portion. From the step of forming a metal layer on the finger by secondary electroforming after this press forming, and the step of peeling the lead frame formed by primary electroforming and secondary electroforming from the substrate. Of manufacturing a semiconductor device lead frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60074299A JPH0722191B2 (en) | 1985-04-10 | 1985-04-10 | Method for manufacturing lead frame of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60074299A JPH0722191B2 (en) | 1985-04-10 | 1985-04-10 | Method for manufacturing lead frame of semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11798392A Division JPH07106481A (en) | 1992-04-10 | 1992-04-10 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61234060A JPS61234060A (en) | 1986-10-18 |
| JPH0722191B2 true JPH0722191B2 (en) | 1995-03-08 |
Family
ID=13543112
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60074299A Expired - Lifetime JPH0722191B2 (en) | 1985-04-10 | 1985-04-10 | Method for manufacturing lead frame of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0722191B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040050682A (en) * | 2002-12-10 | 2004-06-16 | 김정식 | Lead frame by electric pole processing and its manufacturing method |
| WO2004053975A1 (en) * | 2002-12-12 | 2004-06-24 | Graphion Technologies Usa, Llc | Chip-on-film and its methods of manufacturing by electro-forming |
| JP2004214265A (en) * | 2002-12-27 | 2004-07-29 | Kyushu Hitachi Maxell Ltd | Semiconductor device and its manufacturing method |
| JP2013058816A (en) * | 2012-12-28 | 2013-03-28 | Hitachi Maxell Ltd | Intermediate component for semiconductor device and manufacturing method of the same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5462128A (en) * | 1977-10-26 | 1979-05-18 | Hamasawa Kogyo Kk | Peeling of electroforming exterior blade |
| JPS55110051A (en) * | 1979-02-15 | 1980-08-25 | Nec Corp | Lead frame and semiconductor device |
| JPS57171681A (en) * | 1981-04-17 | 1982-10-22 | Toshiba Corp | Lead frame and its manufacture |
-
1985
- 1985-04-10 JP JP60074299A patent/JPH0722191B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61234060A (en) | 1986-10-18 |
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