JPS61234060A - Manufacture of lead frame of semiconductor device - Google Patents

Manufacture of lead frame of semiconductor device

Info

Publication number
JPS61234060A
JPS61234060A JP7429985A JP7429985A JPS61234060A JP S61234060 A JPS61234060 A JP S61234060A JP 7429985 A JP7429985 A JP 7429985A JP 7429985 A JP7429985 A JP 7429985A JP S61234060 A JPS61234060 A JP S61234060A
Authority
JP
Japan
Prior art keywords
lead frame
finger
substrate
electroforming
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7429985A
Other languages
Japanese (ja)
Other versions
JPH0722191B2 (en
Inventor
Hiroshi Shimazu
博士 嶋津
Yasuo Yamashita
康雄 山下
Masayoshi Suzuki
鈴記 正義
Eiji Sakata
栄二 坂田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyushu Hitachi Maxell Ltd
Maxell Ltd
Original Assignee
Kyushu Hitachi Maxell Ltd
Hitachi Maxell Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyushu Hitachi Maxell Ltd, Hitachi Maxell Ltd filed Critical Kyushu Hitachi Maxell Ltd
Priority to JP60074299A priority Critical patent/JPH0722191B2/en
Publication of JPS61234060A publication Critical patent/JPS61234060A/en
Publication of JPH0722191B2 publication Critical patent/JPH0722191B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828Etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49534Multi-layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To readily form a lead frame without using an expensive manufacturing method such as etching even in case of the frame with many fingers by forming the frame with the fingers fundamentally by an electroforming. CONSTITUTION:A resist layer 9 of the desired pattern is formed on a substrate 8, and the shape of a nonresist portion 8a is formed in a lead frame shape of the desired pattern. A metal layer 10 is formed only on the nonresist portion 8a except the layer 9 by electroforming on the substrate 8, and pressed to bend to project at the metal layer side. Then, the layer 10 of a laminate is again electroformed, the second metal layer 11 is laminated, and a contact material 12 is further coated on the end 4d of the finger 4. When only the substrate 8 is eventually separated from the laminate, a lead frame 7 having the finger 4 is obtained. The end 4d of the obtained finger 4 is formed with a bump 4a having a thickness in the projecting direction, and suitable flexibility is applied by a thin erected portion 4c.

Description

【発明の詳細な説明】 〔技術分野〕 本発明はIC,LSI等の半導体チップを固定するのに
用いるリードフレームの製造方法に関する。 〔背景技術〕 従来より半導体チップを樹脂モールドで一体化して複数
ピンを突設した半導体装置の組立てには金属製のリード
フレームが用いられている。このリードフレームは薄い
金属板をプレスで打ち抜いたり、エツチングなどによっ
て形成されており、その形状は第3図に示すように、半
導体チップ1を取り付ける矩形のタブ2をその4隅にお
いて支持するタブリード3と、タブ2の周縁に内端を臨
ませる複数のフィンガ4と、これらフィンガ4及びタブ
リード3の外端を支持する枠部5と、枠部5の両側縁に
沿って定間隔に設けられたスプロケット孔6とからなっ
ている。 このようなリードフレーム7を用いて半導体装置を組立
てるには、まずタブ2上に半導体チップ1を取り付けた
後、半導体チップ1の各電極とこれに対応するフィンガ
4の内端をワイヤあるいはワイヤを用いず直接に接続し
、その後矩形枠部5の内側領域を合成樹脂でモールドし
半導体チップ1を被覆し、次いで枠部5を切除して半導
体装置を得るのである。 ところで、リードフレーム7のフィンガ4の先端は第4
図に示すように半導体チップlの電極1aに半田その他
の手段を用いて接続されるのであるが、一般に電極1a
はミリコンlb上に薄膜状に形成されたアルミニウムパ
ッドからなり、周囲の保護膜ICより凹んだ位置にある
。そこでフィンガ4の先端部には電極1aと接続を容易
にするためバンブ4aが形成されるのであるが、近年に
おいて多数ピンの半導体装置が望まれてくると、フィン
ガ数は同様に増加し、フィンガ4の幅も極めて細いもの
となるため、上記バンブの形成が困難となってきている
。 〔発明の目的〕 本発明は上記の点に鑑みてなされたもので、多数のバン
ブ付フィンガを備えたリードフレームを容易に成形でき
るリードフレームの製造方法の提供を目的としている。 〔発明の概要〕 上記目的を達成するための手段として、本発明は、半導
体チップの電極と接続されるフィンガを導電性金属薄板
にて形成したリードフレームの製造方法であって、少な
くとも表面に導電性を有する金属基板に所望パターンの
レジスト層を形成する工程と、この基板をプレス成形し
てフィンガ基部の先方に起立部を介してフィンガ基部と
略平行な先端部が形成される所望のフィンガ形状を得る
ためのプレス工程と、このプレス成形の後に電鋳により
金属層を形成する工程と、電鋳により形成されたリード
フレームを基板より剥離する工程とからなり、電鋳され
たリードフレームを基板より除去した状態そのままで、
フィンガ先端にバンブ形状が得られるようにしたことを
特徴としている。 〔実施例〕 第1図は本発明の実施例におけるリードフレームの成形
工程を示す図である。 まず第1図(a)の如くステンレス等の導電性金属から
なる基板8上に所望パターンのレジスト層9を形成する
。このレジスト層9はリードフレーム7を形成しない位
置にのみ積層されるものであって・非レジスト部8aの
形状は所望パターンのリードフレーム形状である。  
  次にこの基板8上に、レジストがアルカリ現像タイプで
はカセイソーダを、溶剤タイプの場合は塩化メチレン等
の溶剤を用いて剥離処理を行う。 その後この基板8上に電鋳により銅、ニッケル、金等の
金属を積層させる。これにより(b)図の如くレジスト
層9を除く非レジスト部8a上にのみ金属層10が形状
される。 このようにして一枚の板状に成形された基板8及び金属
層の積層体の一部をプレス成形により(C)図の如く、
金属層側に突出するように折曲加工する。この成形部分
はリードフレーム7の中央部に位置するタブ2及びフィ
ンガ4先端部であって、(C)図ではタブ2に向かって
対向して延出する一対のフィンガ4を示しており、フィ
ンガ4は平坦なフィンガ基部4b、基部4bより上方へ
延びる起立部4 c s及び起立部4cから基部4bと
略平行に延びる先端部4dとをそれぞれ備えている。な
おタブ2は特に必要としない。 次いで、上記の如く変形された積層体の金属層10上に
再び電鋳を施し、(d)図の如き銅、ニッケル等の第2
の金属層11を積層する。この電鋳加工においては、平
坦な基部4b、先端部4dに対して起立部4Cは傾斜し
た位置にあるため、電鋳による金属層11は起立部4C
ではその成長速度が遅い。 また、フィンガ4の先端部4dは細い頚部によって起立
部4Cに連結されているため、電流密度が大きくなり、
金属はこの部分でより成長する。従って、図からもわか
るように起立部4cの肉厚t2は基部4bの肉厚t、よ
り小さく最小で、先端部4dの肉厚t3は最大(tコ>
1.>1.)となる。 更に(81図に示すように、フィンガ4の先端部4dに
は金、すず、半田の如き材料からなる接点材12が塗布
される。この接点材12は半導体チップ1の電極1aと
の接続をより良好にするためのもので、特に必要としな
いがレジスト層13により他の部分を被覆した状態でフ
ィンガ4の先端部4d上面に塗布もしくはメッキを施せ
ばよい。 最後に積層体から基板8のみを剥離すれば、(f)図に
示す如きフィンガ4をもつリードフレーム7が得られる
。得られたフィンガ4の先端部4dはその突出方向に厚
みをもつバンプ4aを構成し、薄肉の起立部4cによっ
て適度な可撓性を与えられることになる。 特に起立部4cの肉厚1.を小さくすることにより、半
導体チップとの接合時の加工力を緩和させて基部4bの
変形、横ずれを防止することができ、この部分をバッフ
ァ領域として使用できる。 このバッファ領域は、先端部4を作るときのプレス加工
によって同時に得られるので、特別な加工を必要とせず
、加工の簡素化が図れる。 第2図は本発明の変形例を示す製造工程説明図である。 即ち、(a)図に示すように、まずはじめに基板8上に
レジスト層9を形成した状態で第一次の電鋳加工を行う
点は第1図の実施例と同様である。但し、基板8の非レ
ジスト部8a上には予め金、すす、半田等の接触材12
を塗布もしくはメッキを施しておく。 次にCb1図に示すように積層体全体にプレス加工を施
し、基板8を突出するようにフィンガ相当部分を折り曲
げる。折り曲げ形状は第1図の実施例と同様に基部4b
、起立部4c、先端部4dから構成されるものであるが
、先端部4dの下面には同時にバンプ4aをプレスによ
り形成する。 次いで金属層10上に第二次の電鋳加工を施し、(C)
図の如き第2の金属層11を金属層lO上に形成する。 この際前述したように先端部4d、基部4b、起立部4
cの順でその肉厚は大きく形成される。 最後に基板8を剥離すれば(d)図の如き形状のフィン
ガ4を有するリードフレーム7が得られる。 特にこの場合には、フィンガ4の、半導体チップと接合
する側が、基板8のプレス形状及び寸法そのままとなる
ため、プレス精度に応じてフィンガ4の精度を向上させ
ることができ、より一層多ピン化に対応できる。 なお上記実施例では、−次及び二次電鋳による二層金属
層を一体として用いたが、−次電鋳と二次電鋳との間に
剥離処理を行い二次電鋳金属層だけを用いてリードフレ
ームを得ることもでき、この時は一次電鋳金属材は例え
ば銅のような二次電鋳材のニッケルと比較して安価な材
質を使用できる。 また、レジスト層9を形成しただけの基板8をまず所望
形状にプレス加工し、その後−次電鋳、もしくは−次電
鋳と二次電鋳をし、基板8からこの電鋳による金属層を
剥離してそのままリードフレームとすることも可能であ
る。 〔発明の効果〕 本発明は以上の通りであり、フィンガを含むリードフレ
ームは基本的に電鋳によって形成されるから、プレス成
形によって打ち抜き成形するのが困難な多数フィンガを
もつリードフレームであっても、エツチング等の高価な
製造方法を用いることなく容易に成形することができる
とともに、フィンガ先端のバンプ及びバンプを支持する
可撓性を有する起立片を第二次の電鋳により同時にかつ
容易に成形することができるものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for manufacturing a lead frame used for fixing semiconductor chips such as ICs and LSIs. [Background Art] Metal lead frames have conventionally been used to assemble semiconductor devices in which semiconductor chips are integrated with resin molding and have a plurality of protruding pins. This lead frame is formed by punching out a thin metal plate with a press or by etching, and its shape is as shown in FIG. , a plurality of fingers 4 whose inner ends face the periphery of the tab 2, a frame 5 that supports these fingers 4 and the outer ends of the tab lead 3, and a plurality of fingers 4 provided at regular intervals along both side edges of the frame 5 It consists of a sprocket hole 6. To assemble a semiconductor device using such a lead frame 7, first attach the semiconductor chip 1 onto the tab 2, and then connect each electrode of the semiconductor chip 1 and the corresponding inner end of the finger 4 with a wire or a wire. After that, the inner region of the rectangular frame portion 5 is molded with synthetic resin to cover the semiconductor chip 1, and then the frame portion 5 is cut out to obtain a semiconductor device. By the way, the tip of the finger 4 of the lead frame 7 is the fourth
As shown in the figure, it is connected to the electrode 1a of the semiconductor chip 1 using solder or other means, but generally the electrode 1a
consists of an aluminum pad formed in the form of a thin film on the millicon lb, and is recessed from the surrounding protective film IC. Therefore, a bump 4a is formed at the tip of the finger 4 to facilitate connection with the electrode 1a. However, as semiconductor devices with multiple pins have become desired in recent years, the number of fingers has similarly increased, and the number of fingers has increased as well. 4 is also extremely narrow, making it difficult to form the bumps. [Object of the Invention] The present invention has been made in view of the above points, and an object of the present invention is to provide a method for manufacturing a lead frame that can easily form a lead frame having a large number of bumped fingers. [Summary of the Invention] As a means to achieve the above object, the present invention provides a method for manufacturing a lead frame in which fingers connected to electrodes of a semiconductor chip are formed of a conductive metal thin plate, the lead frame having conductive metal on at least the surface. a step of forming a resist layer with a desired pattern on a metal substrate having a property, and press-molding this substrate to form a desired finger shape in which a tip portion substantially parallel to the finger base is formed at the tip of the finger base via an upright portion. A step of forming a metal layer by electroforming after this press forming, and a step of peeling the lead frame formed by electroforming from the substrate. As it was removed,
It is characterized by a bump shape at the tip of the finger. [Example] FIG. 1 is a diagram showing a lead frame molding process in an example of the present invention. First, as shown in FIG. 1(a), a resist layer 9 having a desired pattern is formed on a substrate 8 made of a conductive metal such as stainless steel. This resist layer 9 is laminated only at the position where the lead frame 7 is not formed, and the shape of the non-resist portion 8a is the shape of the lead frame of a desired pattern.
Next, a peeling process is performed on this substrate 8 using caustic soda if the resist is an alkaline development type, or using a solvent such as methylene chloride if the resist is a solvent type. Thereafter, metals such as copper, nickel, and gold are laminated on this substrate 8 by electroforming. As a result, the metal layer 10 is formed only on the non-resist portion 8a excluding the resist layer 9, as shown in FIG. Part of the laminate of the substrate 8 and the metal layer thus formed into a single plate is press-molded as shown in Figure (C).
Bend it so that it protrudes toward the metal layer side. These molded parts are the tips of the tab 2 and fingers 4 located in the center of the lead frame 7, and FIG. 4 includes a flat finger base 4b, an upright portion 4cs extending upward from the base 4b, and a tip 4d extending from the upright portion 4c substantially parallel to the base 4b. Note that tab 2 is not particularly required. Next, electroforming is performed again on the metal layer 10 of the laminate deformed as described above, and (d) a second layer of copper, nickel, etc. is applied as shown in the figure.
A metal layer 11 is laminated. In this electroforming process, since the upright part 4C is at an inclined position with respect to the flat base part 4b and the tip part 4d, the electroformed metal layer 11 is formed on the upright part 4C.
Its growth rate is slow. In addition, since the tip portion 4d of the finger 4 is connected to the upright portion 4C by a thin neck, the current density increases,
Metal grows more in this area. Therefore, as can be seen from the figure, the wall thickness t2 of the upright portion 4c is smaller than the wall thickness t of the base portion 4b and is the minimum, and the wall thickness t3 of the tip portion 4d is the maximum (t >
1. >1. ). Furthermore, as shown in FIG. 81, a contact material 12 made of a material such as gold, tin, or solder is applied to the tip 4d of the finger 4. This is to make it even better, and although it is not particularly necessary, coating or plating may be applied to the upper surface of the tip portion 4d of the finger 4 while the other portions are covered with the resist layer 13.Finally, only the substrate 8 is removed from the laminate. By peeling off the lead frame 7, a lead frame 7 having fingers 4 as shown in FIG. 4c provides appropriate flexibility. In particular, by reducing the wall thickness 1 of the upright portion 4c, the processing force during bonding with the semiconductor chip is alleviated, thereby preventing deformation and lateral displacement of the base portion 4b. This part can be used as a buffer area. Since this buffer area can be obtained at the same time by pressing when making the tip part 4, no special processing is required, and the processing can be simplified. FIG. 2 is a manufacturing process explanatory diagram showing a modification of the present invention. That is, as shown in FIG. The procedure is the same as that of the embodiment shown in FIG.
Coating or plating. Next, as shown in Figure Cb1, the entire laminate is pressed, and the portions corresponding to the fingers are bent so that the substrate 8 protrudes. The bent shape is the same as the embodiment shown in FIG.
, an upright portion 4c, and a tip portion 4d, and a bump 4a is simultaneously formed on the lower surface of the tip portion 4d by pressing. Next, a second electroforming process is performed on the metal layer 10, (C)
A second metal layer 11 as shown in the figure is formed on the metal layer IO. At this time, as mentioned above, the tip part 4d, the base part 4b, the upright part 4
The wall thickness increases in the order of c. Finally, by peeling off the substrate 8, a lead frame 7 having fingers 4 having a shape as shown in FIG. 3(d) is obtained. Particularly in this case, the side of the fingers 4 that is bonded to the semiconductor chip has the pressed shape and dimensions of the substrate 8, so the precision of the fingers 4 can be improved in accordance with the press precision, and the number of pins can be further increased. Can correspond to In the above example, two metal layers formed by secondary and secondary electroforming were used as one body, but peeling treatment was performed between secondary electroforming and secondary electroforming to remove only the secondary electroformed metal layer. It is also possible to obtain a lead frame by using the lead frame, and in this case, a material such as copper, which is cheaper than the secondary electroformed material such as nickel, can be used as the primary electroformed metal material. In addition, the substrate 8 on which only the resist layer 9 is formed is first pressed into a desired shape, and then secondary electroforming or secondary electroforming and secondary electroforming are performed to form a metal layer from the substrate 8 by this electroforming. It is also possible to peel it off and use it as a lead frame. [Effects of the Invention] The present invention is as described above, and since the lead frame including the fingers is basically formed by electroforming, it is a lead frame with a large number of fingers that is difficult to punch out by press forming. It can also be easily formed without using expensive manufacturing methods such as etching, and the bump at the tip of the finger and the flexible upright piece that supports the bump can be simultaneously and easily formed by secondary electroforming. It can be molded.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例におけるリードフレームの製造
工程を説明する図、第2図は本発明の他の実施例におけ
るリードフレームの製造工程を説明する図、第3図は本
発明を用いる一般的なリードフレームの平面図、第4図
はフィンガ先端のバンプと半導体チップの電極との関係
を示す断面図である。 l・・・半導体チップ、la・・・電極、2・・・タブ
、4・・・フィンガ、4a・・・バンプ、4b・・・フ
ィンガ基部、4c・・・起立部、4d・・・フィンガ先
端部、7・・・リードフレーム、8・・・基板、8a・
・・非レジスト部、9・・・レジスト層、10・・・金
属層、11・・・金属層。 L  F、’、、::f、’ 、、r 第1図 第2図
FIG. 1 is a diagram explaining the manufacturing process of a lead frame in an embodiment of the present invention, FIG. 2 is a diagram explaining the manufacturing process of a lead frame in another embodiment of the invention, and FIG. 3 is a diagram explaining the manufacturing process of a lead frame in an embodiment of the present invention. FIG. 4, which is a plan view of a typical lead frame, is a sectional view showing the relationship between the bumps at the tips of the fingers and the electrodes of the semiconductor chip. l...Semiconductor chip, la...electrode, 2...tab, 4...finger, 4a...bump, 4b...finger base, 4c...standing portion, 4d...finger Tip part, 7... Lead frame, 8... Substrate, 8a.
... Non-resist portion, 9... Resist layer, 10... Metal layer, 11... Metal layer. L F,',,:f,',,r Fig. 1 Fig. 2

Claims (1)

【特許請求の範囲】[Claims]  半導体チップの電極と接続されるフィンガを導電性金
属薄板にて形成したリードフレームの製造方法であつて
、少なくとも表面に導電性を有する金属基板に所望パタ
ーンのレジスト層を形成する工程と、この基板をプレス
成形してフィンガ基部の先方に起立部を介してフィンガ
基部と略平行な先端部が形成される所望のフィンガ形状
を得るためのプレス工程と、このプレス成形の後に電鋳
により金属層を形成する工程と、電鋳により形成された
リードフレームを基板より剥離する工程とからなる半導
体装置のリードフレーム製造方法。
A method for manufacturing a lead frame in which fingers connected to electrodes of a semiconductor chip are formed from a conductive metal thin plate, the method comprising: forming a resist layer in a desired pattern on a metal substrate having conductivity at least on the surface; A pressing step is carried out to obtain a desired finger shape in which a tip section that is approximately parallel to the finger base is formed through an upright section at the tip of the finger base, and after this press forming, a metal layer is formed by electroforming. A method for manufacturing a lead frame for a semiconductor device, which comprises a step of forming a lead frame and a step of peeling a lead frame formed by electroforming from a substrate.
JP60074299A 1985-04-10 1985-04-10 Method for manufacturing lead frame of semiconductor device Expired - Lifetime JPH0722191B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60074299A JPH0722191B2 (en) 1985-04-10 1985-04-10 Method for manufacturing lead frame of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60074299A JPH0722191B2 (en) 1985-04-10 1985-04-10 Method for manufacturing lead frame of semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP11798392A Division JPH07106481A (en) 1992-04-10 1992-04-10 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS61234060A true JPS61234060A (en) 1986-10-18
JPH0722191B2 JPH0722191B2 (en) 1995-03-08

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Family Applications (1)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004053972A1 (en) * 2002-12-10 2004-06-24 Graphion Technologies Usa Llc Lead frame and the same manufacturing method using electroforming
WO2004053975A1 (en) * 2002-12-12 2004-06-24 Graphion Technologies Usa, Llc Chip-on-film and its methods of manufacturing by electro-forming
JP2011216921A (en) * 2002-12-27 2011-10-27 Kyushu Hitachi Maxell Ltd Semiconductor device and method of manufacturing the same
JP2013058816A (en) * 2012-12-28 2013-03-28 Hitachi Maxell Ltd Intermediate component for semiconductor device and manufacturing method of the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5462128A (en) * 1977-10-26 1979-05-18 Hamasawa Kogyo Kk Peeling of electroforming exterior blade
JPS55110051A (en) * 1979-02-15 1980-08-25 Nec Corp Lead frame and semiconductor device
JPS57171681A (en) * 1981-04-17 1982-10-22 Toshiba Corp Lead frame and its manufacture

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5462128A (en) * 1977-10-26 1979-05-18 Hamasawa Kogyo Kk Peeling of electroforming exterior blade
JPS55110051A (en) * 1979-02-15 1980-08-25 Nec Corp Lead frame and semiconductor device
JPS57171681A (en) * 1981-04-17 1982-10-22 Toshiba Corp Lead frame and its manufacture

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004053972A1 (en) * 2002-12-10 2004-06-24 Graphion Technologies Usa Llc Lead frame and the same manufacturing method using electroforming
WO2004053975A1 (en) * 2002-12-12 2004-06-24 Graphion Technologies Usa, Llc Chip-on-film and its methods of manufacturing by electro-forming
JP2011216921A (en) * 2002-12-27 2011-10-27 Kyushu Hitachi Maxell Ltd Semiconductor device and method of manufacturing the same
JP2013058816A (en) * 2012-12-28 2013-03-28 Hitachi Maxell Ltd Intermediate component for semiconductor device and manufacturing method of the same

Also Published As

Publication number Publication date
JPH0722191B2 (en) 1995-03-08

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