JPS62266844A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS62266844A
JPS62266844A JP11201186A JP11201186A JPS62266844A JP S62266844 A JPS62266844 A JP S62266844A JP 11201186 A JP11201186 A JP 11201186A JP 11201186 A JP11201186 A JP 11201186A JP S62266844 A JPS62266844 A JP S62266844A
Authority
JP
Japan
Prior art keywords
tab
lead
leads
package
tab lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11201186A
Other languages
Japanese (ja)
Inventor
Kazunari Michii
一成 道井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP11201186A priority Critical patent/JPS62266844A/en
Publication of JPS62266844A publication Critical patent/JPS62266844A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To support a tab stably even if the electrodes of a semiconductor element are arranged on the entire surface and to facilitate bonding work, by providing inner leads, which are separated from outer leads, between a tab lead and the end of a package, in a single line type semiconductor device. CONSTITUTION:A tab lead 4' supporting a tab 3 is provided along the longitudinal direction of a package. Inner leads 10, which are separated from outer leads 5, are provided approximately in parallel along the tab lead 4' between the tab lead 4' and the end part of the package. Electrodes 6 of a semiconductor element 2 are once connected to the inner leads 10 with wires 7. Then, the inner leads 10, and the outer connection leads 5 are connected with the wires 7. Then, the electrodes 6 of the semiconductor elements 2 can be connected to the outer connecting leads 5. When the inner leads 10 and the outer connection leads 5 are connected with the wires 7, the wires 7 are bridged over the tab lead 4,. By sinking the tab lead 4', the short circuit risk between the wires 7 and the tab lead 4' is eliminated.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、シングルインライン泣の半導体装置に係り
、特にリードフレームの内部接続用リードの形状に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a single in-line semiconductor device, and particularly to the shape of an internal connection lead of a lead frame.

〔従来の技術〕[Conventional technology]

第２図は従来のシングルインライン型半導体装置の構成
を示す平面図である。同図において、リードフレーム１
は、半導体素子２を搭載するタブ３と、このタブ３を支
え組立工程が終了するまで図示しないフレーム枠に支持
でれるタブリード４と、このタブ３に対して放射状に配
置される複数の外部回路接続用のり−ド５とから構成さ
れておシ、半導体素子２の電極６はワイヤ７によって各
リード５にそれぞれ接続され、前述した半導体素子２．
タブ３．タブリード４およびリード５等の周辺部で点線
に囲まれた領域８が樹脂封止されて第３図に示すように
パッケージ９が形成され、半導体装置が構成はれる。FIG. 2 is a plan view showing the configuration of a conventional single in-line type semiconductor device. In the same figure, lead frame 1
A tab 3 on which a semiconductor element 2 is mounted, a tab lead 4 that supports this tab 3 and is supported by a frame (not shown) until the assembly process is completed, and a plurality of external circuits arranged radially with respect to this tab 3. The electrodes 6 of the semiconductor element 2 are connected to the respective leads 5 by wires 7, and the semiconductor element 2 described above is composed of a connecting lead 5.
Tab 3. A region 8 surrounded by dotted lines around the tab leads 4, leads 5, etc. is sealed with resin to form a package 9 as shown in FIG. 3, and a semiconductor device is constructed.

このように構成されるシングルインライン型半導体装置
は、タブ３を安定して支えるにはパッケージ９の長手方
向に氾って２本のタブリード４を設けることが望ましい
が、外部接続用リード５がパッケージ９の一方向から導
出しているため、外部接続用リード５はタブリード４を
超えて形成することはできない。このため、半導体素子
２の全周部分に電極６が形成された場合にはボンディン
グ作業ができなくなるので、一般的には第２図に示すよ
うに半導体素子２の３辺の端部に電極６が形成されてい
る。In a single in-line semiconductor device configured as described above, it is desirable to provide two tab leads 4 extending in the longitudinal direction of the package 9 in order to stably support the tab 3; Since the lead 9 is led out from one direction, the external connection lead 5 cannot be formed beyond the tab lead 4. For this reason, if the electrodes 6 are formed all around the semiconductor element 2, the bonding operation cannot be performed, so generally, the electrodes 6 are formed at the ends of three sides of the semiconductor element 2, as shown in FIG. is formed.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、このように構成されるシングルインライ
ン型半導体装置は、半導体素子２の全周にわたって電極
６が配列されている場合、第４図に示すよりに外部リー
ド５の配列と反対側にタブリード４を設けることは可能
であるが、タブ３の寸法が大きい場合、タブ３が極めて
不安定となシ、タブ３の傾き等により、ワイヤ７のボン
ディング作業が不安定となるという問題が生じる。また
、パッケージ９内のタブリード４が外気と接近するため
、パッケージ９内に湿気が浸入し易くなるなどの問題が
あった。However, in a single in-line semiconductor device configured in this way, when the electrodes 6 are arranged all around the semiconductor element 2, the tab leads 4 are placed on the opposite side of the arrangement of the external leads 5 as shown in FIG. However, if the size of the tab 3 is large, the problem arises that the tab 3 is extremely unstable, and the inclination of the tab 3 makes the bonding operation of the wire 7 unstable. Further, since the tab lead 4 inside the package 9 comes close to the outside air, there is a problem that moisture easily enters the inside of the package 9.

この発明は、前述した従来の問題を解決するためになさ
れたもので、半導体素子の電極が全周にわたって配列さ
れていてもタブを安定に支え、かつボンディング作業も
容易にできる半導体装置を提供することを目的としてい
る。This invention was made to solve the above-mentioned conventional problems, and provides a semiconductor device that can stably support a tab even when the electrodes of a semiconductor element are arranged all around the circumference, and that can facilitate bonding work. The purpose is to

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係わる半導体装置は、タブリードとパンケー
ジ端部との間に、外部リードと分離した内部リードを設
けたものである。A semiconductor device according to the present invention is provided with an internal lead separated from an external lead between the tab lead and the end of the pan cage.

〔作用〕[Effect]

この発明においては、内部リードと、半導体素子の１！
極および外部リードとがワイヤによりｉ続される。In this invention, the internal lead and the semiconductor element 1!
The pole and the external lead are connected by a wire.

〔実施例〕〔Example〕

以下、図面を用いてこの発明の詳細な説明する０ 第１図はこの発明による半導体装置の一実施例を示す平
面図であシ、前述の図と同一部分には同一符号を付しで
ある。同図において、タブ３を支持するタブリード４′
はパッケージの長手方向に泊って設けられてお夛、この
タブリード４′とパッケージの端部との間には、外部リ
ード５と分離された内部リード１０がタブリード４′に
泊ってほぼ平行に設けられている。この内部リード１０
は図示しないフレーム枠によって支えられており、樹脂
封止後に切断される。The present invention will be described in detail below with reference to the drawings. FIG. 1 is a plan view showing an embodiment of a semiconductor device according to the present invention, and the same parts as in the previous figures are given the same reference numerals. . In the figure, a tab lead 4' supporting the tab 3 is shown.
are provided along the longitudinal direction of the package, and between this tab lead 4' and the end of the package, an internal lead 10 separated from the external lead 5 is provided approximately parallel to the tab lead 4'. It is being This internal lead 10
is supported by a frame (not shown), and is cut after resin sealing.

このような構成に２いて、半導体素子２の電極６は、−
問この内部リード１０にワイヤ７で接続し、次にこの内
部リード１０と外部接続用リード５とをワイヤ７で接続
することにより、半導体素子２の’！ＩＩ極６と外部接
伏用リード５との接続が可能となる。また、内部リード
１０と外部接続用リード５と紮ワイヤ７で接続する場合
、ワイヤ７がタブリード４′を悩絡する構成となるが、
タブリード４′を沈め加工することにより、タブリード
４′の上面が内部リード１０ｉ６よひ外部接続用リード
５の上面より下っていれば、ワイヤ７とタブリード４′
　との短絡の危険性はなくなる。In such a configuration 2, the electrode 6 of the semiconductor element 2 is -
Q: By connecting this internal lead 10 with the wire 7, and then connecting this internal lead 10 and the external connection lead 5 with the wire 7, the semiconductor element 2'! Connection between the II pole 6 and the external grounding lead 5 becomes possible. Further, when connecting the internal lead 10 and the external connection lead 5 with the ligature wire 7, the wire 7 becomes a problem with the tab lead 4'.
By sinking the tab lead 4', if the top surface of the tab lead 4' is lower than the top surface of the internal lead 10i6 and the external connection lead 5, the wire 7 and the tab lead 4'
There is no risk of short circuit with the

〔兆明の効果〕[Chomei effect]

以上説明したようにこの発明によれば、タブを安定しで
支え、かつボンディング作業が容易となシ、半導体素子
のシングルインラインタイプのパッケージへの適用範囲
が拡大される等の極めて優れた効果が得られる。As explained above, according to the present invention, the tab can be stably supported, the bonding work can be facilitated, and the range of application to single-in-line type packages for semiconductor devices can be expanded. can get.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明による半導体装置の一実施例を説明す
る平面図、第２図ないし第４図は従来の半導体装置を説
明する図である。 １・・・・リードフレーム、２・―φ・半導体素子、３
・・Φ・タブ、４′　・・・・タブリード、５・・・・
外部接続用リード、６・拳・自電極、７・曝・・ワイヤ
、８・・・ｅ拉１脂封止領域、９・・・拳パッケージ、
１０・・・・内部リード。FIG. 1 is a plan view illustrating an embodiment of a semiconductor device according to the present invention, and FIGS. 2 to 4 are diagrams illustrating conventional semiconductor devices. 1...Lead frame, 2--φ semiconductor element, 3
...Φ・Tab, 4' ...Tab lead, 5...
Lead for external connection, 6. Fist/own electrode, 7. Exposed wire, 8... Era 1 grease sealing area, 9... Fist package,
10...Internal lead.

Claims (1)

【特許請求の範囲】[Claims] 　半導体素子を搭載するタブと、このタブ周辺に配置さ
れ前記半導体素子の電極にワイヤを介して接続される複
数のリードと、その周辺部を樹脂封止したパッケージと
を備え、前記リードが前記パッケージの主面に並行に所
定間隔で一方向から導出される半導体装置において、前
記タブをフレーム枠に支持するタブリードを中心として
前記リード群と対峙するタブとパッケージ端部との間に
前記リードと分離された内部リードを設け、前記半導体
素子の電極および前記リードと前記内部リードとをワイ
ヤにより接続したことを特徴とする半導体装置。The tab includes a tab on which a semiconductor element is mounted, a plurality of leads arranged around the tab and connected to electrodes of the semiconductor element via wires, and a package whose peripheral portion is sealed with resin, and the lead is attached to the package. In a semiconductor device that is led out from one direction at a predetermined interval parallel to the main surface of a semiconductor device, a tab lead that supports the tab on a frame is the center, and a space between the tab facing the group of leads and the end of the package is separated from the lead. What is claimed is: 1. A semiconductor device, characterized in that an internal lead is provided, and the electrode of the semiconductor element and the lead are connected to the internal lead by a wire.
JP11201186A 1986-05-14 1986-05-14 Semiconductor device Pending JPS62266844A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11201186A JPS62266844A (en) 1986-05-14 1986-05-14 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11201186A JPS62266844A (en) 1986-05-14 1986-05-14 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS62266844A true JPS62266844A (en) 1987-11-19

Family

ID=14575734

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11201186A Pending JPS62266844A (en) 1986-05-14 1986-05-14 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS62266844A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63199450A (en) * 1987-02-16 1988-08-17 Nippon Denso Co Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63199450A (en) * 1987-02-16 1988-08-17 Nippon Denso Co Ltd Semiconductor device

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