JPS622348B2 - - Google Patents

Info

Publication number
JPS622348B2
JPS622348B2 JP10145282A JP10145282A JPS622348B2 JP S622348 B2 JPS622348 B2 JP S622348B2 JP 10145282 A JP10145282 A JP 10145282A JP 10145282 A JP10145282 A JP 10145282A JP S622348 B2 JPS622348 B2 JP S622348B2
Authority
JP
Japan
Prior art keywords
bus
master device
signal
clock
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP10145282A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58219627A (ja
Inventor
Akira Hoshino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Fuji Facom Corp
Original Assignee
Fuji Electric Co Ltd
Fuji Facom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, Fuji Facom Corp filed Critical Fuji Electric Co Ltd
Priority to JP10145282A priority Critical patent/JPS58219627A/ja
Publication of JPS58219627A publication Critical patent/JPS58219627A/ja
Publication of JPS622348B2 publication Critical patent/JPS622348B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
JP10145282A 1982-06-15 1982-06-15 バスシステム Granted JPS58219627A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10145282A JPS58219627A (ja) 1982-06-15 1982-06-15 バスシステム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10145282A JPS58219627A (ja) 1982-06-15 1982-06-15 バスシステム

Publications (2)

Publication Number Publication Date
JPS58219627A JPS58219627A (ja) 1983-12-21
JPS622348B2 true JPS622348B2 (de) 1987-01-19

Family

ID=14301082

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10145282A Granted JPS58219627A (ja) 1982-06-15 1982-06-15 バスシステム

Country Status (1)

Country Link
JP (1) JPS58219627A (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0321628B1 (de) * 1987-12-23 1992-11-04 International Business Machines Corporation Gemeinsam genutzte Speicherschnittstelle für Datenverarbeitungsanlage
JPH0934830A (ja) * 1995-07-21 1997-02-07 Nec Shizuoka Ltd バスマスタ回路
JP3293733B2 (ja) * 1996-01-29 2002-06-17 甲府日本電気株式会社 共通バス制御装置
US6658580B1 (en) * 2000-05-20 2003-12-02 Equipe Communications Corporation Redundant, synchronous central timing systems with constant master voltage controls and variable slave voltage controls

Also Published As

Publication number Publication date
JPS58219627A (ja) 1983-12-21

Similar Documents

Publication Publication Date Title
EP0135879B1 (de) Interface-Schaltung und Verfahren zum Verbinden einer Speichersteuereinrichtung mit einem synchronen oder asynchronen Bussystem
JP3565600B2 (ja) データ通信装置およびデータ通信方法
JP2711035B2 (ja) マルチクロック同期プロセッサユニット
GB2143060A (en) Data processing system
JPH0619756B2 (ja) 非同期装置間で通信を行なうための効率的なプロトコル
JPS63303454A (ja) バス拡張制御方式
JPH0578849B2 (de)
JPS622348B2 (de)
JPS589461B2 (ja) マルチプロセッサ・システム
EP1489521B1 (de) Zugang von zwei synchronen Bussen mit asynchronem Takt zu einem synchronen Einport-RAM
JPS62226260A (ja) 非同期式デ−タバスインタ−フエ−ス
JPS61177564A (ja) 共有記憶装置
JPH08180027A (ja) 調停回路
JPH0756645B2 (ja) データ処理装置
JPH06282525A (ja) 同期型バス装置
JPS581917Y2 (ja) 複数記憶回路の位相同期回路
JPH02280263A (ja) マイクロプロセッサ
JPS581811B2 (ja) ダイレクト・メモリ・アクセス制御方式
JPS6341973A (ja) マルチプロセツサシステム
JPH06149749A (ja) 複数プロセッサ間におけるデータ転送方式
JPH03144739A (ja) 二重化記憶装置へのデータ転写制御方式
JPH0551931B2 (de)
JPH10289202A (ja) マイコン回路
JPH0521253B2 (de)
JPS62211763A (ja) 同期出力回路