JPS62225042A - Bit synchronizing circuit - Google Patents

Abstract

PURPOSE:To prevent missing of data even when the repetitive frequency of the lst and 2nd clock signals approaches by adopting a 1/n frequency division circuit (n>=4) for the frequency division circuit. CONSTITUTION:A digital signal inputted to an input terminal 11 is shifted at a shift register 31 by using the lst clock signal from an input terminal 12. Further, the lst clock signal is subject to l/n frequency division (n>=4) by the frequency division circuit 14 and a load pulse is outputted to a memory circuit 16 via a load pulse generating circuit 32 and the circuit 16 stores the output of the circuit 31 by N-bit simultaneously. Further, the output of the circuit 14 is subject to retiming by a re-timing circuit 15 by using the 2nd clock signal from the input terminal 13 and the result is inputted to a set pulse generating circuit 33. Then the n-set of outputs of the circuit 16 and a missing clock generating circuit 18 are inputted to a shift register 34 from which a data is outputted serially. Thus, even if jitter takes place in each clock signal, missing of data is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bit synchronization circuit for a time division multiplex communication system.

[Conventional technology]

FIG. 4 is a circuit diagram showing an example of the configuration of a conventional bit synchronization circuit disclosed in, for example, Japanese Patent Application Laid-Open No. 60-40747.

(a), (b), ((ri,・
Characters such as . . . indicate positions of timing waveforms represented by the same characters in FIG. 5 shown later. In the figure, lυ is the input terminal of the digital signal, (L2 is the input terminal of the first clock signal whose bit phase is synchronized with the digital signal and has a repetition frequency f1, and Q3 is the input terminal of the first clock signal whose bit phase is synchronized with the digital signal and whose repetition frequency is f2. This is the input terminal for the second clock signal of the terminal.Furthermore, Q4 is a divide-by-2 counter, and Q9 is an α
A retiming circuit that uses the output of a as a data input and the clock input to the input terminal C13 as a trigger input, fl
[9 is an elastic ink memory having a capacity of 2 bits, which alternately stores the input signal 1 bit at a time while being controlled by the output of the 2-frequency divider counter.
/f1 period. Furthermore, (aη is a selection circuit that is controlled by the output of Q9 and selects one of the two outputs of 0Q, and 08 is a pulse generator that has the function of generating an output at the time when the output of the retiming circuit α changes. be.

With this configuration, the output terminal α9 has the input terminal α
A digital signal whose phase is synchronized with the clock signal input to the output terminal is outputted, and a pulse synchronized with the digital signal outputted to the output terminal αj is outputted to the output terminal (1). The relationship between the repetition frequency f1 of the first clock signal input from input terminal α2 and the repetition frequency f of the second clock signal input from input terminal a3 is [f
4 and 5, the operation when f2 is higher than l, but approximately equal, and the changing points of both are close to each other will be explained with reference to FIGS. 4 and 5.

In the figure, (a) is the input clock of the frequency divider circuit α, and (b) (CJ is the output of the frequency divided by 2. The input digital signal (d) is input to the memory circuit αQ (b) (
By C), one bit is alternately stored in two memories, resulting in (e) and (f). Further, (b) is retimed by a retiming circuit (clock signal transmission of repetition frequency f2 at I!9). In Figure 5 (the arrow marked in bJ indicates the changing point of the timing waveform in (b))
This indicates whether the timing is before or after the rising edge of the waveform.

The left arrow points to the front, and the right arrow points to the rear.

Retiming circuit a! In 9, data whose arrows point outward from each other is not retimed once, and data whose arrows point inward from each other are retimed twice, and the output waveform becomes (1). (h) is a phase-inverted version of (1). The selection circuit αη uses (h) and (1) as selection signals to select the data strings (8J and (f)) stored in the memory circuit 0I and outputs the digital signal (4). 4, the data of data numbers 2 and 4 are dropped.Also, in the pulse generating circuit a8, there is no case where the level of (b) is not alternately inverted at the bit break of the digital signal (t), so the digital signal < 1)
The corresponding pulse is not generated.

[Problem that the invention seeks to solve]

Since the conventional bit synchronization circuit is configured as described above, f2 is sufficiently higher than 1 and the change point of the output from the divide-by-2 circuit I and the rise of the trigger input in the retiming circuit aS in FIG. This is only effective if the data input can be retimed more than once even when the data inputs are close to each other or overlap.

There is a problem in that data may be dropped if this condition is not met.

The present invention has been made to solve the above problems, and the repetition frequency of a first clock signal phase-synchronized with a digital signal and a second clock signal having a higher repetition frequency than the first clock are close to each other. An object of the present invention is to obtain a bit synchronization circuit that does not cause data dropout even when data is lost.

[Failure to solve the problem]

The bit synchronization circuit according to the present invention replaces the 1-frequency divider with an n-divider (n''4), uses the memory circuit as an n-bit memory circuit, and arranges shift registers before and after the memory circuit to control input data signals. The data is written to the memory circuit in parallel in units of n bits.

[Effect]

By using the n frequency divider circuit (n24) as the frequency divider circuit in this invention, the output of the frequency divider circuit can be controlled by the retiming circuit even if the change point of the frequency divider output and the rise of the trigger input are close to each other or overlap. Retimed at least once to prevent data loss.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a bit synchronization circuit according to the present invention.

In the figure, am is an input terminal for a digital signal, a is an input terminal for a first clock signal that is bit synchronized with the digital signal, and α is an input terminal for a second clock signal for bit synchronization. be. Input terminal α2 and 0
0 Since the input conditions of each clock signal are the same as those shown in FIG. 4, the repetition frequency of each is also f, .
Let it be f2. 0υ is a shift register (I
4 is a frequency dividing circuit that divides the first clock signal from the input terminal 02 by n, G2 is a load pulse generating circuit that generates a low pulse from the output of the frequency dividing circuit I, and (le is from (to) The load pulse causes the shift register 0
α9 is an n-bit memory circuit that stores the output from the frequency dividing circuit α, and
This is a retiming circuit that performs retiming using the clock signal. Further, (to) is a set pulse generation circuit that generates a data set permission pulse from the output of the retiming circuit, and α barrel is a set pulse generation circuit that generates a clock signal from the output of the set pulse generation circuit (to). The clock generation circuit C341 sets n outputs of the n-bit memory circuit aQ based on the data set permission nox from the seven-bit nox generation circuit (to). The tooth extraction from the square is a shift register that outputs data serially based on a clock signal. +19 again
is an output terminal of a digital signal that is phase-synchronized with the second clock signal of the input terminal (13), and is an output terminal of a clock signal that is synchronized with the digital signal outputted to the output terminal α9.

FIG. 2 is an example showing a specific circuit configuration of the block diagram shown in FIG. 1, and is for n-4. In FIG. 2, parts assigned the same numbers as those used in FIG. 1 represent the same contents as each part in FIG. FIG. 3 is a timing diagram showing waveforms of various parts in FIG. 2.

The circuit operation according to the present invention will be explained in detail below with reference to FIGS. 2 and 3. Note that (g) in FIG.

Characters such as (a), (!:)), etc. indicate the positions of timing waveforms represented by the same characters in FIG. 3, which will be shown later.

In Fig. 2, the input digital signal (f) input from the input terminal αυ is transferred to the input terminal Q3 by the shift register 6D.
shifted by a first clock signal (7) from
Soft), ni), ni) and (a). The first clock signal (7) from the input terminal α2 is frequency-divided by four in the frequency dividing circuit α4 to become (to) and (a). The output (1) from the frequency dividing circuit I passes through a NOR gate in the load pulse generating circuit (1) and becomes a load pulse. The output data string (seconds) to ■ from the shift register 0η is simultaneously stored in 4 bits in the memory circuit by the first clock signal (7) from the input terminal aΔ and the load pulse (7) from the load pulse generation circuit (to). ni) ふ, (b), V) and ni). The retention time of the memory circuit (data string C:l in II) is 4/f1.

The output (1) from the frequency divider circuit (14) is the retiming circuit a! At 9, the input terminal (1: retimed by the second clock signal (b) from I becomes ()), and further retimed by the inverted clock of (c)). The arrow marked in (a) of FIG. 3 indicates whether the changing point of the timing waveform in (a) is before or after the rise of the second clock signal (to). The output (G) of the retiming circuit r1S is shifted by 1 bit and inverted by 1 by the inverted clock (G) in the set pulse generation circuit (to).
(g)), and (b) and (b) pass through the OR gate to become a 1-bit wide set pulse (b). The set pulse from the set pulse generation circuit (to) is shifted by 1 bit by the inverted clock of (b) in the clock generation circuit +Is, and becomes (7), which is the nant game i1.
It becomes (g) through. The change point (g) usually appears every two bits. (G) is further 1 with the inverted clock of (B).
Bit-shifted, it becomes (g), and by taking the exclusive sum of (g) and the example, it becomes ). 2) becomes a pulse (S) whose level is alternately inverted at the change point of the data string No. 0 which is shifted by 1 bit by the inverted clock of (to) and output from the shift register (B) described later. ) passes through the Nant gate and becomes an inhibit pulse corresponding to the digital signal (c) which is used to generate a clock signal. The clock signal diagram is inhibited by the second clock signal (2) from the input terminal α4 and corresponds to the digital signal e. After the memory circuit (four outputs from IG) are set simultaneously by the set pulse (-:/) from the set pulse generation circuit in the shift register (b), the tooth extraction is performed by the clock generation circuit 08. The tooth extraction from the clock signal V) is serially outputted as an output digital signal e.

In the above embodiment, the output of the frequency divider circuit 0, which is input to the load pulse generating circuit 02, is sent to the retiming circuit Q! 19
The case of retiming was shown in .

All cases of retiming using pulses generated by the frequency divider circuit 0 are within the scope of the present invention.

[Effects of the Invention] As described above, according to the present invention, the repetition periods of the first clock signal synchronized with the input digital signal and the second clock signal for bit synchronization approach equalization, and each Even if the operating speed of the signal is close to the limit of the circuit element capability and even if some jitter occurs in each clock signal, data dropout can be prevented.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the present invention, and FIG. 2 is a circuit diagram showing an embodiment of the circuit configuration of the present invention. Fig. 3 is a timing diagram for explaining the operation of the circuit diagram shown in Fig. 2, Fig. 4 is a circuit diagram showing an example of a conventional bit synchronization circuit, and Fig. 5 is an operation of the circuit diagram shown in Fig. 4. This is a timing diagram for explaining. aυ is the input terminal for the digital signal, az is the input terminal for the first clock signal, 03 is the input terminal for the second clock signal, I is the frequency dividing circuit, O5 is the retiming circuit, αQ is the memory circuit, and the pin is the tooth. 09 is a clock generation circuit, O9 is a digital signal output terminal, (A) is a clock signal output terminal, and 0υ is a shift register. C(side) is a load pulse generation circuit, (to) is a set pulse generation circuit, ((匈) is a shift register. In the two figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] an input terminal for a digital signal, an input terminal for a first clock phase synchronized with the digital signal, an input terminal for a second clock having a repetition frequency higher than the repetition frequency of the first clock; a shift register that shifts according to the first clock;
a frequency dividing circuit that divides the first clock by n (n≧4); a load pulse generating circuit that generates a load pulse from the output of the frequency dividing circuit; and n bits that store the shift register output using the load pulse. a memory circuit, a retiming circuit that retimes the output of the frequency divider circuit with the second clock, a set pulse generation circuit that generates a data set permission pulse based on the output of the retiming circuit, and an output of the set pulse generation circuit. a toothless clock generation circuit that generates a toothless clock signal from a toothless clock generator; and n outputs of the n-bit memory circuit are set based on the output of the set pulse generation circuit, and data is serially generated by the output of the toothless clock generation circuit. A bit synchronization circuit characterized in that it is equipped with a shift register that outputs an output to a shift register.